{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T16:58:38Z","timestamp":1725382718108},"reference-count":8,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,4]]},"DOI":"10.1109\/coolchips.2012.6216583","type":"proceedings-article","created":{"date-parts":[[2012,6,21]],"date-time":"2012-06-21T08:18:10Z","timestamp":1340266690000},"page":"1-3","source":"Crossref","is-referenced-by-count":0,"title":["A 5.184Gbps\/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors"],"prefix":"10.1109","author":[{"given":"Yasuhisa","family":"Shimazaki","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Noriyuki","family":"Miura","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tadahiro","family":"Kuroda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","first-page":"256","article-title":"3D system integration of processor and multi-stacked SRAMs by using inductive-coupling links","author":"osada","year":"2009","journal-title":"IEEE Symposium on VLSI Circuits Dig Tech Papers"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2009.4977517"},{"key":"1","first-page":"36","article-title":"Power efficient and high performance processor for mobile applications","author":"shimazaki","year":"2011","journal-title":"JSPS and IEEE International Symposium on Low Power VLSI Design Proceedings"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2010.5560299"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2009.5357248"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280819"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523175"},{"key":"8","first-page":"490","article-title":"A 2.7Gb\/s\/mm2 0.9pJ\/b\/chip 1coil\/channel thruchip interface with coupled-resonator-based CDR for NAND flash memory stacking","author":"miura","year":"2011","journal-title":"ISSCC Dig Tech Papers"}],"event":{"name":"2012 IEEE Cool Chips XV","start":{"date-parts":[[2012,4,18]]},"location":"Yokohama, Japan","end":{"date-parts":[[2012,4,20]]}},"container-title":["2012 IEEE COOL Chips XV"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6210529\/6216568\/06216583.pdf?arnumber=6216583","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T12:44:08Z","timestamp":1490100248000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6216583\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,4]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/coolchips.2012.6216583","relation":{},"subject":[],"published":{"date-parts":[[2012,4]]}}}