{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,13]],"date-time":"2024-09-13T05:55:33Z","timestamp":1726206933839},"reference-count":3,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,4]]},"DOI":"10.1109\/coolchips.2014.6842954","type":"proceedings-article","created":{"date-parts":[[2014,7,28]],"date-time":"2014-07-28T17:04:42Z","timestamp":1406567082000},"page":"1-3","source":"Crossref","is-referenced-by-count":12,"title":["A Perpetuum Mobile 32bit CPU with 13.4pJ\/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology"],"prefix":"10.1109","author":[{"given":"Koichiro","family":"Ishibashi","sequence":"first","affiliation":[]},{"given":"Nobuyuki","family":"Sugii","sequence":"additional","affiliation":[]},{"given":"Kimiyoshi","family":"Usami","sequence":"additional","affiliation":[]},{"given":"Hideharu","family":"Amano","sequence":"additional","affiliation":[]},{"given":"Kazutoshi","family":"Kobayashi","sequence":"additional","affiliation":[]},{"family":"Cong-Kha Pham","sequence":"additional","affiliation":[]},{"given":"Hideki","family":"Makiyama","sequence":"additional","affiliation":[]},{"given":"Yoshiki","family":"Yamamoto","sequence":"additional","affiliation":[]},{"given":"Hirofumi","family":"Shinohara","sequence":"additional","affiliation":[]},{"given":"Toshiaki","family":"Iwamatsu","sequence":"additional","affiliation":[]},{"given":"Yasuo","family":"Yamaguchi","sequence":"additional","affiliation":[]},{"given":"Hidekazu","family":"Oda","sequence":"additional","affiliation":[]},{"given":"Takumi","family":"Hasegawa","sequence":"additional","affiliation":[]},{"given":"Shinobu","family":"Okanishi","sequence":"additional","affiliation":[]},{"given":"Hiroshi","family":"Yanagita","sequence":"additional","affiliation":[]},{"given":"Shiro","family":"Kamohara","sequence":"additional","affiliation":[]},{"given":"Masaru","family":"Kadoshima","sequence":"additional","affiliation":[]},{"given":"Keiichi","family":"Maekawa","sequence":"additional","affiliation":[]},{"given":"Tomohiro","family":"Yamashita","sequence":"additional","affiliation":[]},{"family":"Duc-Hung Le","sequence":"additional","affiliation":[]},{"given":"Takumu","family":"Yomogita","sequence":"additional","affiliation":[]},{"given":"Masaru","family":"Kudo","sequence":"additional","affiliation":[]},{"given":"Kuniaki","family":"Kitamori","sequence":"additional","affiliation":[]},{"given":"Shuya","family":"Kondo","sequence":"additional","affiliation":[]},{"given":"Yuuki","family":"Manzawa","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5433921"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176932"},{"key":"1","article-title":"Ultralow-voltage operation of silicon-on-thin-BOX (SOTB) 2Mbit SRAM down to 0.37 v utilizing adaptive back bias","author":"yamamoto","year":"2013","journal-title":"VLSI Technology Symposium"}],"event":{"name":"2014 IEEE COOL Chips XVII (COOL Chips)","start":{"date-parts":[[2014,4,14]]},"location":"Yokohama, Japan","end":{"date-parts":[[2014,4,16]]}},"container-title":["2014 IEEE COOL Chips XVII"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6832910\/6842936\/06842954.pdf?arnumber=6842954","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T16:36:39Z","timestamp":1490286999000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6842954\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,4]]},"references-count":3,"URL":"https:\/\/doi.org\/10.1109\/coolchips.2014.6842954","relation":{},"subject":[],"published":{"date-parts":[[2014,4]]}}}