{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,16]],"date-time":"2026-03-16T10:08:29Z","timestamp":1773655709915,"version":"3.50.1"},"reference-count":5,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,4]]},"DOI":"10.1109\/coolchips.2014.6842959","type":"proceedings-article","created":{"date-parts":[[2014,7,28]],"date-time":"2014-07-28T17:04:42Z","timestamp":1406567082000},"page":"1-3","source":"Crossref","is-referenced-by-count":1,"title":["A task-level pipelined many-SIMD augmented reality processor with congestion-aware network-on-chip scheduler"],"prefix":"10.1109","author":[{"given":"Gyeonghoon","family":"Kim","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Seongwook Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Kyuho Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Youchang","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Injoon Hong","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Kyeongryeol Bong","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Dongjoo Shin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Sungpill Choi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Junyoung","family":"Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Hoi-Jun Yoo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176983"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ISMAR.2003.1240686"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2186157"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757391"},{"key":"4","first-page":"168","article-title":"A 646GOPS\/W multi-classifier many-core processor with cortex-like architecture for super-resolution recognition","author":"park","year":"2013","journal-title":"ISSCC Dig Tech Papers 9 8"}],"event":{"name":"2014 IEEE COOL Chips XVII (COOL Chips)","location":"Yokohama, Japan","start":{"date-parts":[[2014,4,14]]},"end":{"date-parts":[[2014,4,16]]}},"container-title":["2014 IEEE COOL Chips XVII"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6832910\/6842936\/06842959.pdf?arnumber=6842959","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T16:36:40Z","timestamp":1490287000000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6842959\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,4]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/coolchips.2014.6842959","relation":{},"subject":[],"published":{"date-parts":[[2014,4]]}}}