{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,28]],"date-time":"2025-06-28T06:23:36Z","timestamp":1751091816310},"reference-count":6,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,4]]},"DOI":"10.1109\/coolchips.2019.8721304","type":"proceedings-article","created":{"date-parts":[[2019,5,27]],"date-time":"2019-05-27T19:51:16Z","timestamp":1558986676000},"page":"1-3","source":"Crossref","is-referenced-by-count":8,"title":["Statistical Access Interval Prediction for Tightly Coupled Memory Systems"],"prefix":"10.1109","author":[{"given":"Robert","family":"Wittig","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mattis","family":"Hasler","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Emil","family":"Matus","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gerhard","family":"Fettweis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2591513.2591569"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/SAMOS.2013.6621138"},{"key":"ref6","article-title":"A tightly-coupled multi-core cluster with shared-memory HW accelerators","author":"dehyadegari","year":"2012","journal-title":"SAMOS"},{"key":"ref5","article-title":"A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters","author":"rahimi","year":"2011","journal-title":"DATE"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062188"},{"journal-title":"TI","article-title":"OMAP 4 mobile applications platform","year":"2011","key":"ref1"}],"event":{"name":"2019 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","start":{"date-parts":[[2019,4,17]]},"location":"Yokohama, Japan","end":{"date-parts":[[2019,4,19]]}},"container-title":["2019 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8713395\/8721298\/08721304.pdf?arnumber=8721304","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,14]],"date-time":"2022-07-14T23:07:32Z","timestamp":1657840052000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8721304\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,4]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/coolchips.2019.8721304","relation":{},"subject":[],"published":{"date-parts":[[2019,4]]}}}