{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T03:02:22Z","timestamp":1725591742146},"reference-count":7,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,4]]},"DOI":"10.1109\/coolchips.2019.8721336","type":"proceedings-article","created":{"date-parts":[[2019,5,27]],"date-time":"2019-05-27T23:51:16Z","timestamp":1559001076000},"page":"1-3","source":"Crossref","is-referenced-by-count":1,"title":["Multi-Level Packet Processing Caches"],"prefix":"10.1109","author":[{"given":"Kyosuke","family":"Tanaka","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hayato","family":"Yamaki","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shinobu","family":"Miwa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroki","family":"Honda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2016.7869977"},{"journal-title":"Cisco Nexus 9500 R-Series Line Cards and Fabric Modules White Paper","article-title":"Cisco","year":"0","key":"ref3"},{"journal-title":"MAWI working group traffic archive","article-title":"WIDE MAWI Working Group","year":"0","key":"ref6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.33"},{"key":"ref7","first-page":"110:1","article-title":"Data Prediction for Response Flows in Packet Processing Cache","author":"yamaki","year":"2018","journal-title":"Proc of the 55th Annual Design Automation Conference DAC ‘18"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS.2016.7804005"},{"journal-title":"NLANR AMP Data","article-title":"Réseaux IP Européens Network Coordination Centre","year":"0","key":"ref1"}],"event":{"name":"2019 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","start":{"date-parts":[[2019,4,17]]},"location":"Yokohama, Japan","end":{"date-parts":[[2019,4,19]]}},"container-title":["2019 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8713395\/8721298\/08721336.pdf?arnumber=8721336","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,15]],"date-time":"2022-07-15T03:07:32Z","timestamp":1657854452000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8721336\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,4]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/coolchips.2019.8721336","relation":{},"subject":[],"published":{"date-parts":[[2019,4]]}}}