{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T13:10:09Z","timestamp":1725628209173},"reference-count":6,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,4,14]],"date-time":"2021-04-14T00:00:00Z","timestamp":1618358400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,4,14]],"date-time":"2021-04-14T00:00:00Z","timestamp":1618358400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,4,14]]},"DOI":"10.1109\/coolchips52128.2021.9410314","type":"proceedings-article","created":{"date-parts":[[2021,4,29]],"date-time":"2021-04-29T20:08:37Z","timestamp":1619726917000},"page":"1-3","source":"Crossref","is-referenced-by-count":1,"title":["Nonvolatile SRAM Using Fishbone-in-Cage Capacitor in a 180 nm Standard CMOS Process for Zero-Standby and Instant-Powerup Embedded Memory on IoT"],"prefix":"10.1109","author":[{"given":"Takaki","family":"Urabe","sequence":"first","affiliation":[{"name":"Kyoto Institute of Technology,Kyoto,Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroyuki","family":"Ochi","sequence":"additional","affiliation":[{"name":"Ritsumeikan University,Kusatsu,Japan,Shiga"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kazutoshi","family":"Kobayashi","sequence":"additional","affiliation":[{"name":"Kyoto Institute of Technology,Kyoto,Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/NVSMW.2008.30"},{"key":"ref3","first-page":"9","article-title":"Thereshold-voltage Measurement of CMOS-compatible Non-volatile Memory Element using FiCC and Consideration on its Readout Method","author":"tanaka","year":"0","journal-title":"Design Automation Symposium"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2012.6213624"},{"key":"ref5","first-page":"87","article-title":"Energy performance of nonvolatile power-gating SRAM using SOTB technology","author":"shuto","year":"0","journal-title":"ES-SCIRC Conference"},{"key":"ref2","first-page":"43","article-title":"FiCC: Crosstalk Noise Hardened Metal Fringe Capacitor for High Integration","author":"tanaka","year":"2017","journal-title":"IE-ICE Technical Report VLD2018&#x2013;65"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.2970118"}],"event":{"name":"2021 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","start":{"date-parts":[[2021,4,14]]},"location":"Tokyo, Japan","end":{"date-parts":[[2021,4,16]]}},"container-title":["2021 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9410308\/9410309\/09410314.pdf?arnumber=9410314","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,8,3]],"date-time":"2022-08-03T00:20:26Z","timestamp":1659486026000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9410314\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,4,14]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/coolchips52128.2021.9410314","relation":{},"subject":[],"published":{"date-parts":[[2021,4,14]]}}}