{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T13:52:09Z","timestamp":1730209929873,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,4,14]],"date-time":"2021-04-14T00:00:00Z","timestamp":1618358400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,4,14]],"date-time":"2021-04-14T00:00:00Z","timestamp":1618358400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,4,14]],"date-time":"2021-04-14T00:00:00Z","timestamp":1618358400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,4,14]]},"DOI":"10.1109\/coolchips52128.2021.9410326","type":"proceedings-article","created":{"date-parts":[[2021,4,29]],"date-time":"2021-04-29T20:08:37Z","timestamp":1619726917000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["A Timing Aware Connectivity Optimization Technique for Improving Energy Efficiency of High-Performance CPUs"],"prefix":"10.1109","author":[{"given":"Ayan","family":"Datta","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Karanvir","family":"Singh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Arpita","family":"Dutta","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kousik","family":"Debnath","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Dfm challenges and solutions for 14nm finfet","year":"0","author":"dhanani","key":"ref10"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2011.09.011"},{"key":"ref12","article-title":"14 nm process technology: Opening new horizons","author":"bohr","year":"2014","journal-title":"Intel Developer Forum"},{"journal-title":"Algorithms for VLSI Physical Design Automation","year":"2012","author":"sherwani","key":"ref13"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313908"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2181796.2181798"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"415","DOI":"10.1109\/81.841927","article-title":"Clock-gating and its application to low power design of sequential circuits","volume":"47","author":"wu","year":"2000","journal-title":"IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications"},{"journal-title":"Method and apparatus to configure thermal design power in a microprocessor","year":"2015","author":"distefano","key":"ref5"},{"journal-title":"Parasitic capacitance extraction for finfets","year":"2014","author":"ho","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2614004"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1974.1050511"},{"key":"ref1","article-title":"Ai and compute","author":"amodei","year":"2018","journal-title":"Heruntergeladen von"},{"key":"ref9","first-page":"1144","article-title":"Design-Synthesis Co-Optimisation Using Skewed and Tapered Gates","author":"ayan datta","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"}],"event":{"name":"2021 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","start":{"date-parts":[[2021,4,14]]},"location":"Tokyo, Japan","end":{"date-parts":[[2021,4,16]]}},"container-title":["2021 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9410308\/9410309\/09410326.pdf?arnumber=9410326","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T15:40:44Z","timestamp":1652197244000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9410326\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,4,14]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/coolchips52128.2021.9410326","relation":{},"subject":[],"published":{"date-parts":[[2021,4,14]]}}}