{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,26]],"date-time":"2025-11-26T16:44:07Z","timestamp":1764175447586},"reference-count":12,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,4,19]],"date-time":"2023-04-19T00:00:00Z","timestamp":1681862400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,4,19]],"date-time":"2023-04-19T00:00:00Z","timestamp":1681862400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,4,19]]},"DOI":"10.1109\/coolchips57690.2023.10121985","type":"proceedings-article","created":{"date-parts":[[2023,5,15]],"date-time":"2023-05-15T17:53:16Z","timestamp":1684173196000},"page":"1-6","source":"Crossref","is-referenced-by-count":2,"title":["A 2.41-\u03bcW\/MHz, 437-PE\/mm<sup>2<\/sup> CGRA in 22 nm FD-SOI With RISC-Like Code Generation"],"prefix":"10.1109","author":[{"given":"Tobias","family":"Kaiser","sequence":"first","affiliation":[{"name":"Technische Universit&#x00E4;t,Chair of Mixed Signal Circuit Design,Berlin,Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Friedel","family":"Gerfers","sequence":"additional","affiliation":[{"name":"Technische Universit&#x00E4;t,Chair of Mixed Signal Circuit Design,Berlin,Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"The RISC-V instruction set manual volume I User-level ISA document version 2019121","year":"2019","author":"waterman","key":"ref8"},{"key":"ref7","doi-asserted-by":"crossref","DOI":"10.1109\/CGO.2004.1281665","article-title":"LLVM: A compilation framework for lifelong program analysis & transformation","author":"lattner","year":"2004","journal-title":"International Symposium on Code Generation and Optimization"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46769.2022.9830509"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1002\/spe.774"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-21867-5_3"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446703"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2016.7838029"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/A-SSCC47793.2019.9056954"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/277652.277659"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3056219"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00046"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1749603.1749604"}],"event":{"name":"2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","start":{"date-parts":[[2023,4,19]]},"location":"Tokyo, Japan","end":{"date-parts":[[2023,4,21]]}},"container-title":["2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10121902\/10121921\/10121985.pdf?arnumber=10121985","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,6,19]],"date-time":"2023-06-19T17:43:15Z","timestamp":1687196595000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10121985\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,4,19]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/coolchips57690.2023.10121985","relation":{},"subject":[],"published":{"date-parts":[[2023,4,19]]}}}