{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T13:52:17Z","timestamp":1730209937259,"version":"3.28.0"},"reference-count":18,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,4,19]],"date-time":"2023-04-19T00:00:00Z","timestamp":1681862400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,4,19]],"date-time":"2023-04-19T00:00:00Z","timestamp":1681862400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,4,19]]},"DOI":"10.1109\/coolchips57690.2023.10122117","type":"proceedings-article","created":{"date-parts":[[2023,5,15]],"date-time":"2023-05-15T17:53:16Z","timestamp":1684173196000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Cachet: A High-Performance Joint-Subtree Integrity Verification for Secure Non-Volatile Memory"],"prefix":"10.1109","author":[{"given":"Tatsuya","family":"Kubo","sequence":"first","affiliation":[{"name":"The University of Tokyo,Tokyo,Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shinya","family":"Takamaeda-Yamazaki","sequence":"additional","affiliation":[{"name":"The University of Tokyo,Tokyo,Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2003.1183547"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2019.00114"},{"journal-title":"Update the root of integrity tree in secure non-volatile memory systems with low overhead","year":"2021","author":"huang","key":"ref15"},{"journal-title":"Intel optane persistent memory","year":"2020","key":"ref14"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322250"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00040"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253207"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1150019.1136502"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/3185768.3185771"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00049"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322252"},{"key":"ref7","first-page":"1","article-title":"Secnvm: An efficient and write-friendly metadata crash consistency scheme for secure nvm","volume":"19","author":"lei","year":"2021","journal-title":"ACM Transactions on Architecture and Code Optimization (TACO)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-40061-5_12"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.16"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2020.3020085"},{"key":"ref6","article-title":"Cachetree: Reducing integrity verification overhead of secure non-volatile memories","author":"chen","year":"2020","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"ref5","first-page":"1","article-title":"Intel sgx explained","volume":"2016","author":"costan","year":"2016","journal-title":"IACR Cryptol ePrint Arch"}],"event":{"name":"2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","start":{"date-parts":[[2023,4,19]]},"location":"Tokyo, Japan","end":{"date-parts":[[2023,4,21]]}},"container-title":["2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10121902\/10121921\/10122117.pdf?arnumber=10122117","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,6,12]],"date-time":"2023-06-12T17:51:35Z","timestamp":1686592295000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10122117\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,4,19]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/coolchips57690.2023.10122117","relation":{},"subject":[],"published":{"date-parts":[[2023,4,19]]}}}