{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T16:07:24Z","timestamp":1781885244952,"version":"3.54.5"},"reference-count":0,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,4,16]],"date-time":"2025-04-16T00:00:00Z","timestamp":1744761600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,4,16]],"date-time":"2025-04-16T00:00:00Z","timestamp":1744761600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,4,16]]},"DOI":"10.1109\/coolchips65488.2025.11018599","type":"proceedings-article","created":{"date-parts":[[2025,6,11]],"date-time":"2025-06-11T15:41:35Z","timestamp":1749656495000},"page":"1-6","source":"Crossref","is-referenced-by-count":2,"title":["A Compute-in-Memory Ascon Implementation Based on a Novel 11T SRAM Processing Macro"],"prefix":"10.1109","author":[{"given":"Mark","family":"Lee","sequence":"first","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology,Atlanta,Georgia,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chris","family":"Clark","sequence":"additional","affiliation":[{"name":"Georgia Tech Research Institute,Atlanta,Georgia,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Saibal","family":"Mukhopadhyay","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology,Atlanta,Georgia,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","event":{"name":"2025 IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL CHIPS)","location":"Tokyo, Japan","start":{"date-parts":[[2025,4,16]]},"end":{"date-parts":[[2025,4,18]]}},"container-title":["2025 IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL CHIPS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11018504\/11018539\/11018599.pdf?arnumber=11018599","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,11]],"date-time":"2025-06-11T15:41:36Z","timestamp":1749656496000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11018599\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,4,16]]},"references-count":0,"URL":"https:\/\/doi.org\/10.1109\/coolchips65488.2025.11018599","relation":{},"subject":[],"published":{"date-parts":[[2025,4,16]]}}}