{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,17]],"date-time":"2026-06-17T05:58:34Z","timestamp":1781675914605,"version":"3.54.5"},"reference-count":6,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,4,15]],"date-time":"2026-04-15T00:00:00Z","timestamp":1776211200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,4,15]],"date-time":"2026-04-15T00:00:00Z","timestamp":1776211200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,4,15]]},"DOI":"10.1109\/coolchips68842.2026.11557077","type":"proceedings-article","created":{"date-parts":[[2026,6,16]],"date-time":"2026-06-16T19:41:30Z","timestamp":1781638890000},"page":"1-3","source":"Crossref","is-referenced-by-count":0,"title":["MicroXPU: An Energy-Efficient Low-bit LLM Accelerator with Microscaling Format-Tailored Digital Compute-in-Memory Macro"],"prefix":"10.1109","author":[{"given":"Jiwon","family":"Choi","sequence":"first","affiliation":[{"name":"Korea Advanced Institute of Science and Technology (KAIST),School of EE,Daejeon,Republic of Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Seongyon","family":"Hong","sequence":"additional","affiliation":[{"name":"Korea Advanced Institute of Science and Technology (KAIST),School of EE,Daejeon,Republic of Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Wooyoung","family":"Jo","sequence":"additional","affiliation":[{"name":"Korea Advanced Institute of Science and Technology (KAIST),School of EE,Daejeon,Republic of Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Wonhoon","family":"Park","sequence":"additional","affiliation":[{"name":"Korea Advanced Institute of Science and Technology (KAIST),School of EE,Daejeon,Republic of Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sunjoo","family":"Whang","sequence":"additional","affiliation":[{"name":"Korea Advanced Institute of Science and Technology (KAIST),School of EE,Daejeon,Republic of Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Seryeong","family":"Kim","sequence":"additional","affiliation":[{"name":"Korea Advanced Institute of Science and Technology (KAIST),School of EE,Daejeon,Republic of Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jongjun","family":"Park","sequence":"additional","affiliation":[{"name":"Korea Advanced Institute of Science and Technology (KAIST),School of EE,Daejeon,Republic of Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sangjin","family":"Kim","sequence":"additional","affiliation":[{"name":"Korea Advanced Institute of Science and Technology (KAIST),School of EE,Daejeon,Republic of Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hoi-Jun","family":"Yoo","sequence":"additional","affiliation":[{"name":"Korea Advanced Institute of Science and Technology (KAIST),School of EE,Daejeon,Republic of Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","first-page":"566","article-title":"34.1 A 28nm 83.23 TFLOPS\/W POSIT-Based Compute in-Memory Macro for High-Accuracy AI Applications","volume":"2024","author":"Wang","journal-title":"ISSCC"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/isscc49657.2024.10454308"},{"key":"ref3","first-page":"1","article-title":"14.2 A 16nm 216kb, 188.4 TOPS\/W and 133.5 TFLOPS\/W Microscaling Multi-Mode Gain-Cell CIM Macro Edge AI Devices","author":"Khwa","journal-title":"ISSCC 2025"},{"key":"ref4","article-title":"Microscaling data formats for deep learning","author":"Rouhani","year":"2023"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42615.2023.10067527"},{"key":"ref6","first-page":"570","article-title":"34.3 A 22nm 64kb Lightning-Like Hybrid Computing in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs","author":"Guo","journal-title":"ISSCC 2024"}],"event":{"name":"2026 IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL CHIPS)","location":"Tokyo, Japan","start":{"date-parts":[[2026,4,15]]},"end":{"date-parts":[[2026,4,17]]}},"container-title":["2026 IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL CHIPS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11556509\/11556514\/11557077.pdf?arnumber=11557077","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,17]],"date-time":"2026-06-17T05:47:34Z","timestamp":1781675254000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11557077\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,4,15]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/coolchips68842.2026.11557077","relation":{},"subject":[],"published":{"date-parts":[[2026,4,15]]}}}