{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,20]],"date-time":"2026-02-20T18:55:46Z","timestamp":1771613746620,"version":"3.50.1"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,7]]},"DOI":"10.1109\/csndsp.2014.6923960","type":"proceedings-article","created":{"date-parts":[[2014,10,22]],"date-time":"2014-10-22T20:13:31Z","timestamp":1414008811000},"page":"919-922","source":"Crossref","is-referenced-by-count":3,"title":["A novel PLL lock and out-of-lock detect scheme based on a feedback sampling of PLL"],"prefix":"10.1109","author":[{"given":"Muhammad Kalimuddin","family":"Khan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kenneth","family":"Mulvaney","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","author":"blanchard","year":"1976","journal-title":"Phase-Locked Loops Application to Coherent Receiver Design"},{"key":"2","article-title":"Phase-locked loop design fundamentals","author":"nash","year":"1970","journal-title":"Motorola AN-535"},{"key":"10","author":"goldman","year":"2002","journal-title":"PLL Lock Detection Using A Cycle Slip Detector with Clock Presence Detection"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/41.544547"},{"key":"7","article-title":"A fast Locking-in and low jitter PLL with a process immune locking-in monitor","volume":"pp","author":"li","year":"2013","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"6","first-page":"423","article-title":"A fast locking PLL with phase error detector","author":"kuo","year":"2005","journal-title":"Proc IEEE Conf Electron Devices Solid-State Circuits"},{"key":"5","first-page":"826","article-title":"An adaptive bandwidth phase locked loop with locking status indicator","author":"choi","year":"2005","journal-title":"Proc 9th Russian-Korean Int Symp Sci Technol"},{"key":"4","author":"khan","year":"2013","journal-title":"An Apparatus and Method for Evaluating the Performance of A System in A Control Loop"},{"key":"9","author":"ahn","year":"2002","journal-title":"Phase Lock Detection Circuit for Phase-locked Loop Circuit"},{"key":"8","author":"ishibashi","year":"2004","journal-title":"Lock Detector and Phase Locked Loop Circuit"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/4.509859"}],"event":{"name":"2014 9th International Symposium on Communication Systems, Networks & Digital Signal Processing (CSNDSP)","location":"Manchester, UK","start":{"date-parts":[[2014,7,23]]},"end":{"date-parts":[[2014,7,25]]}},"container-title":["2014 9th International Symposium on Communication Systems, Networks &amp; Digital Sign (CSNDSP)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6913114\/6923783\/06923960.pdf?arnumber=6923960","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T21:27:27Z","timestamp":1490304447000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6923960\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,7]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/csndsp.2014.6923960","relation":{},"subject":[],"published":{"date-parts":[[2014,7]]}}}