{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,20]],"date-time":"2026-05-20T16:22:58Z","timestamp":1779294178628,"version":"3.51.4"},"reference-count":37,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,7,31]],"date-time":"2023-07-31T00:00:00Z","timestamp":1690761600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,7,31]],"date-time":"2023-07-31T00:00:00Z","timestamp":1690761600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,7,31]]},"DOI":"10.1109\/csr57506.2023.10224984","type":"proceedings-article","created":{"date-parts":[[2023,8,28]],"date-time":"2023-08-28T17:50:16Z","timestamp":1693245016000},"page":"572-579","source":"Crossref","is-referenced-by-count":2,"title":["A New Fast and Side-Channel Resistant AES Hardware Architecture"],"prefix":"10.1109","author":[{"given":"Marco","family":"Macchetti","sequence":"first","affiliation":[{"name":"Kudelski Security, Kudelski Group,Cheseaux-sur-Lausanne,Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Herv\u00e9","family":"Pelletier","sequence":"additional","affiliation":[{"name":"IoT Security Labs, Kudelski Group,Cheseaux-sur-Lausanne,Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"C\u00e9dric","family":"Groux","sequence":"additional","affiliation":[{"name":"Nagravision, Kudelski Group,Cheseaux-sur-Lausanne,Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-45146-4_27"},{"key":"ref35","year":"0","journal-title":"Vivado Design Suite 7 Series FPGA and Zynq-7000 SoC Libraries Guide"},{"key":"ref12","first-page":"95","article-title":"An Efficient Side-Channel Protected AES Implementation with Arbitrary Protection Order","author":"gro?","year":"0","journal-title":"Proceedings of CT-RSA 2017"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-28632-5_1"},{"key":"ref15","first-page":"1","article-title":"Generic Low-Latency Masking in Hardware","volume":"2","author":"gro?","year":"2018","journal-title":"IACR Transactions on Cryptographic Hardware and Embedded Systems"},{"key":"ref37","first-page":"323","article-title":"Generic Hardware Private Circuits: Towards Automated Generation of Composable Secure Gadgets","volume":"1","author":"knichel","year":"2022","journal-title":"IACR Transactions on Cryptographic Hardware and Embedded Systems"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-99766-3_10"},{"key":"ref36","first-page":"16","article-title":"Correlation power analysis with a leakage model","author":"brier","year":"0","journal-title":"Proceedings of CHES 2004"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.878344"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2019.00048"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/s00145-010-9085-7"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2020.i3.454-482"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/11545262_12"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/3526241.3530324"},{"key":"ref2","article-title":"Breakthrough AES Performance with Intel® AES New Instructions","author":"akdemir","year":"2010","journal-title":"Intel White Paper"},{"key":"ref1","article-title":"Advanced Encryption Standard (AES)","year":"2001","journal-title":"FIPS Publication 197"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-99766-3_12"},{"key":"ref16","first-page":"589","article-title":"Automated Generation of Masked Hardware","volume":"1","author":"knichel","year":"2022","journal-title":"IACR Transactions on Cryptographic Hardware and Embedded Systems"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2021.i2.61-105"},{"key":"ref18","year":"0","journal-title":"Global Platform SESIP An optimized security evaluation methodology designed for IoT devices"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2015.7140251"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2022.i4.693-717"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2023.3274619"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2019.00002"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-36492-7_17"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2020.i2.300-326"},{"key":"ref21","first-page":"279","article-title":"Side-Channel Analysis of the Xilinx Zynq UltraScale+ Encryption Engine","volume":"1","author":"hettwer","year":"2021","journal-title":"IACR Transactions on Cryptographic Hardware and Embedded Systems"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-30436-1_24"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1007\/11545262_32"},{"key":"ref29","first-page":"731","article-title":"Area and Power Efficient Synthesis of DPA-Resistant Cryptographic S-Boxes","author":"giaconia","year":"2007","journal-title":"VLSI Design"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268856"},{"key":"ref7","first-page":"33","article-title":"Generic Side-Channel Countermeasures for Reconfigurable Devices","author":"g\u00fcneysu","year":"0","journal-title":"proceedings of CHES 2011"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-48405-1_26"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-71817-0_10"},{"key":"ref3","year":"2023","journal-title":"OpenTitan AES HWIP Technical Specification"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.3390\/s22218096"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.6028\/NIST.GCR.18-017"}],"event":{"name":"2023 IEEE International Conference on Cyber Security and Resilience (CSR)","location":"Venice, Italy","start":{"date-parts":[[2023,7,31]]},"end":{"date-parts":[[2023,8,2]]}},"container-title":["2023 IEEE International Conference on Cyber Security and Resilience (CSR)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10224900\/10224823\/10224984.pdf?arnumber=10224984","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,25]],"date-time":"2023-09-25T17:51:23Z","timestamp":1695664283000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10224984\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,7,31]]},"references-count":37,"URL":"https:\/\/doi.org\/10.1109\/csr57506.2023.10224984","relation":{},"subject":[],"published":{"date-parts":[[2023,7,31]]}}}