{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,21]],"date-time":"2026-07-21T14:49:13Z","timestamp":1784645353378,"version":"3.55.0"},"reference-count":19,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,7,1]],"date-time":"2020-07-01T00:00:00Z","timestamp":1593561600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,7,1]],"date-time":"2020-07-01T00:00:00Z","timestamp":1593561600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,7,1]],"date-time":"2020-07-01T00:00:00Z","timestamp":1593561600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,7]]},"DOI":"10.1109\/dac18072.2020.9218691","type":"proceedings-article","created":{"date-parts":[[2020,10,9]],"date-time":"2020-10-09T19:57:03Z","timestamp":1602273423000},"page":"1-6","source":"Crossref","is-referenced-by-count":16,"title":["SAT-Sweeping Enhanced for Logic Synthesis"],"prefix":"10.1109","author":[{"given":"Luca","family":"Amaru","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Felipe","family":"Marranghello","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Eleonora","family":"Testa","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Christopher","family":"Casares","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Vinicius","family":"Possani","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jiong","family":"Luo","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Patrick","family":"Vuillod","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Alan","family":"Mishchenko","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Giovanni","family":"De Micheli","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","article-title":"Fraigs: A unifying representation for logic synthesis and verification","author":"Mishchenko","year":"2005"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.804386"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146970"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2006.320087"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2015.2476472"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203799"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2068716.2068720"},{"key":"ref8","article-title":"Sat-based generation of optimum function implementations with xor gates","author":"Fi\u0161er","year":"2017","journal-title":"Euromicro DSD"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391605"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147044"},{"key":"ref11","article-title":"A robust functional eco engine by sat proof minimization and interpolation techniques","author":"Wu","year":"2010","journal-title":"ICCAD"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.358021"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687546"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2015.7085428"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196111"},{"key":"ref16","first-page":"30","article-title":"A study of sweeping algorithms in the context of model checking","author":"Hassan","year":"2011","journal-title":"Ganesh Gopalakrishnan University of Utah USA"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1993.580110"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2004.1337587"},{"key":"ref19","article-title":"Applying logic synthesis for speeding up sat","volume-title":"Conf. on Theory and Applications of SAT Testing","volume":"4","author":"Niklas Een"}],"event":{"name":"2020 57th ACM\/IEEE Design Automation Conference (DAC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2020,7,20]]},"end":{"date-parts":[[2020,7,24]]}},"container-title":["2020 57th ACM\/IEEE Design Automation Conference (DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9211868\/9218488\/09218691.pdf?arnumber=9218691","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,24]],"date-time":"2024-01-24T01:20:08Z","timestamp":1706059208000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9218691\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,7]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/dac18072.2020.9218691","relation":{},"subject":[],"published":{"date-parts":[[2020,7]]}}}