{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T14:47:19Z","timestamp":1730213239812,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,12,5]],"date-time":"2021-12-05T00:00:00Z","timestamp":1638662400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,12,5]],"date-time":"2021-12-05T00:00:00Z","timestamp":1638662400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,12,5]],"date-time":"2021-12-05T00:00:00Z","timestamp":1638662400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,12,5]]},"DOI":"10.1109\/dac18074.2021.9586129","type":"proceedings-article","created":{"date-parts":[[2021,11,8]],"date-time":"2021-11-08T23:30:34Z","timestamp":1636414234000},"page":"601-606","source":"Crossref","is-referenced-by-count":4,"title":["MELOPPR: Software\/Hardware Co-design for Memory-efficient Low-latency Personalized PageRank"],"prefix":"10.1109","author":[{"given":"Lixiang","family":"Li","sequence":"first","affiliation":[]},{"given":"Yao","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Zacharie","family":"Zirnheld","sequence":"additional","affiliation":[]},{"given":"Pan","family":"Li","sequence":"additional","affiliation":[]},{"given":"Cong","family":"Hao","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.14778\/2732232.2732238"},{"journal-title":"The PageRank Citation Ranking Bringing Order to the Web","year":"1999","author":"page","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2952653"},{"journal-title":"SNAP Datasets Stanford large network dataset collection","year":"2014","author":"leskovec","key":"ref13"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2983323.2983713"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3360902"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3183713.3196920"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2623330.2623745"},{"key":"ref8","first-page":"640","article-title":"GraphH: A processing-in-memory architecture for large-scale graph processing","volume":"38","author":"dai","year":"2018","journal-title":"IEEE TCAD"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3097983.3098072"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2339530.2339538"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/775152.775191"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.14778\/2733085.2733103"}],"event":{"name":"2021 58th ACM\/IEEE Design Automation Conference (DAC)","start":{"date-parts":[[2021,12,5]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2021,12,9]]}},"container-title":["2021 58th ACM\/IEEE Design Automation Conference (DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9585997\/9586083\/09586129.pdf?arnumber=9586129","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T16:55:52Z","timestamp":1652201752000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9586129\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,12,5]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/dac18074.2021.9586129","relation":{},"subject":[],"published":{"date-parts":[[2021,12,5]]}}}