{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,19]],"date-time":"2025-11-19T07:05:17Z","timestamp":1763535917456,"version":"3.28.0"},"reference-count":26,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,12,5]],"date-time":"2021-12-05T00:00:00Z","timestamp":1638662400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,12,5]],"date-time":"2021-12-05T00:00:00Z","timestamp":1638662400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,12,5]],"date-time":"2021-12-05T00:00:00Z","timestamp":1638662400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,12,5]]},"DOI":"10.1109\/dac18074.2021.9586132","type":"proceedings-article","created":{"date-parts":[[2021,11,8]],"date-time":"2021-11-08T23:30:34Z","timestamp":1636414234000},"page":"871-876","source":"Crossref","is-referenced-by-count":8,"title":["LUT-Based Optimization For ASIC Design Flow"],"prefix":"10.1109","author":[{"given":"Luca","family":"Amaru","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vinicius","family":"Possani","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eleonora","family":"Testa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Felipe","family":"Marranghello","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christopher","family":"Casares","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jiong","family":"Luo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Patrick","family":"Vuillod","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alan","family":"Mishchenko","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Giovanni","family":"De Micheli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","article-title":"FRAIGs: A unifying representation for logic synthesis and verification","author":"mishchenko","year":"2005","journal-title":"tech rep ERL Technical Report"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3268344"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/5.52213"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/43.3211"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-3154-8_3"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342108"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8714776"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2068716.2068720","article-title":"Scalable don&#x2019;t-care-based logic optimization and resynthesis","volume":"4","author":"mishchenko","year":"2011","journal-title":"ACM Transactions on Reconfigurable Technology and Systems"},{"journal-title":"Synthesis and Optimization of Digital Circuits","year":"1994","author":"micheli","key":"ref18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/240518.240555"},{"key":"ref4","article-title":"The EPFL combinational benchmark suite","author":"amar\u00fa","year":"2015","journal-title":"Proc of the International Workshop on Logic Synthesis"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/360276.360298"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923088"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/127601.127670"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275118"},{"key":"ref7","article-title":"Support-reducing decomposition for FPGA mapping","author":"machado","year":"2018","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/43.273754"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2007.4397290"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887925"},{"journal-title":"Anonymous","year":"0","key":"ref20"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1956.tb03835.x"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4613-2821-6"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/41.19078"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/12.795224"},{"journal-title":"SIS A system for sequential circuit synthesis","year":"1992","author":"sentovich","key":"ref26"},{"key":"ref25","doi-asserted-by":"crossref","first-page":"24","DOI":"10.1007\/978-3-642-14295-6_5","article-title":"ABC: An academic industrial-strength verification tool","author":"brayton","year":"2010","journal-title":"International Conference on Computer Aided Verification"}],"event":{"name":"2021 58th ACM\/IEEE Design Automation Conference (DAC)","start":{"date-parts":[[2021,12,5]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2021,12,9]]}},"container-title":["2021 58th ACM\/IEEE Design Automation Conference (DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9585997\/9586083\/09586132.pdf?arnumber=9586132","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T16:55:56Z","timestamp":1652201756000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9586132\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,12,5]]},"references-count":26,"URL":"https:\/\/doi.org\/10.1109\/dac18074.2021.9586132","relation":{},"subject":[],"published":{"date-parts":[[2021,12,5]]}}}