{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T16:07:52Z","timestamp":1781885272461,"version":"3.54.5"},"reference-count":21,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,12,5]],"date-time":"2021-12-05T00:00:00Z","timestamp":1638662400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,12,5]],"date-time":"2021-12-05T00:00:00Z","timestamp":1638662400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,12,5]],"date-time":"2021-12-05T00:00:00Z","timestamp":1638662400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100005144","name":"Qualcomm","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100005144","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,12,5]]},"DOI":"10.1109\/dac18074.2021.9586194","type":"proceedings-article","created":{"date-parts":[[2021,11,8]],"date-time":"2021-11-08T23:30:34Z","timestamp":1636414234000},"page":"1183-1188","source":"Crossref","is-referenced-by-count":51,"title":["Designing a 2048-Chiplet, 14336-Core Waferscale Processor"],"prefix":"10.1109","author":[{"given":"Saptadeep","family":"Pal","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jingyang","family":"Liu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Irina","family":"Alam","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Nicholas","family":"Cebry","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Haris","family":"Suhail","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shi","family":"Bu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Subramanian S.","family":"Iyer","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sudhakar","family":"Pamarti","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Rakesh","family":"Kumar","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Puneet","family":"Gupta","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","year":"2020","journal-title":"Ryzen&#x2122; Threadripper&#x2122; Processors"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358302"},{"key":"ref12","article-title":"The BaseJump Manycore Accelerator Network","author":"xie","year":"2018","journal-title":"arXiv 1808 00650 [cs AR]"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2019.00093"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC32862.2020.00358"},{"key":"ref15","year":"2020","journal-title":"Clock Distribution and Balancing Methodology For Large and Complex ASIC Designs"},{"key":"ref16","article-title":"An all-digital 50% duty-cycle corrector","author":"wang","year":"2004","journal-title":"IEEE International Symposium on Circuits and Systems"},{"key":"ref17","year":"2020","journal-title":"Electrostatic discharge (ESD) in 3D-IC packages"},{"key":"ref18","article-title":"A fault-tolerant and deadlock-free routing protocol in 2D meshes based on odd-even turn model","author":"wu","year":"2003","journal-title":"IEEE Transactions on Computers"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/BF01598958"},{"key":"ref4","article-title":"Fast Stencil-Code Computation on a Wafer-Scale Processor","author":"rocki","year":"2020","journal-title":"arXiv 2010 03660"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00047"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2010.5536970"},{"key":"ref5","article-title":"Architecting Waferscale Processors - A GPU Case Study","author":"pal","year":"2019","journal-title":"IEEE International Symposium on High-Performance Comp Architecture"},{"key":"ref8","author":"ramalingam","year":"2020","journal-title":"3D-ICs Advances in the industry"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2018.00288"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/CCGrid.2013.85"},{"key":"ref1","year":"2020","journal-title":"Workload Analysis of Blue Waters"},{"key":"ref9","year":"2020","journal-title":"A100 TENSOR CORE GPU"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2016.7519330"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIT.2017.7998198"}],"event":{"name":"2021 58th ACM\/IEEE Design Automation Conference (DAC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2021,12,5]]},"end":{"date-parts":[[2021,12,9]]}},"container-title":["2021 58th ACM\/IEEE Design Automation Conference (DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9585997\/9586083\/09586194.pdf?arnumber=9586194","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T16:55:53Z","timestamp":1652201753000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9586194\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,12,5]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/dac18074.2021.9586194","relation":{},"subject":[],"published":{"date-parts":[[2021,12,5]]}}}