{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,26]],"date-time":"2026-03-26T16:03:29Z","timestamp":1774541009044,"version":"3.50.1"},"reference-count":20,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,12,5]],"date-time":"2021-12-05T00:00:00Z","timestamp":1638662400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,12,5]],"date-time":"2021-12-05T00:00:00Z","timestamp":1638662400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,12,5]],"date-time":"2021-12-05T00:00:00Z","timestamp":1638662400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100005651","name":"Computing Research Association","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100005651","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,12,5]]},"DOI":"10.1109\/dac18074.2021.9586242","type":"proceedings-article","created":{"date-parts":[[2021,11,8]],"date-time":"2021-11-08T23:30:34Z","timestamp":1636414234000},"page":"229-234","source":"Crossref","is-referenced-by-count":17,"title":["Securing Hardware via Dynamic Obfuscation Utilizing Reconfigurable Interconnect and Logic Blocks"],"prefix":"10.1109","author":[{"given":"Gaurav","family":"Kolhe","sequence":"first","affiliation":[]},{"given":"Soheil","family":"Salehi","sequence":"additional","affiliation":[]},{"given":"Tyler David","family":"Sheaves","sequence":"additional","affiliation":[]},{"given":"Houman","family":"Homayoun","sequence":"additional","affiliation":[]},{"given":"Setareh","family":"Rafatirad","sequence":"additional","affiliation":[]},{"given":"Manoj P D","family":"Sai","sequence":"additional","affiliation":[]},{"given":"Avesta","family":"Sasan","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317831"},{"key":"ref11","article-title":"Interlock: An intercorrelated logic and routing locking","author":"kamali","year":"2020","journal-title":"Proceedings of the 39th International Conference on Computer-Aided Design ser ICCAD ’20"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942100"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3299874.3318038"},{"key":"ref14","article-title":"FPGA architecture: Survey and challenges","author":"kuon","year":"2008","journal-title":"Foundations and Trends in Electronic Design Automation"},{"key":"ref15","article-title":"Scalable Adaptive Spintronic Reconfigurable Logic using Area-Matched MTJ Design","author":"zand","year":"2015","journal-title":"IEEE Transactions on Circuits and Systems II Express Briefs revision pending"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2802870"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2019.2934471"},{"key":"ref18","author":"fazekas","year":"2020","journal-title":"On SAT-based solution methods for computational problems"},{"key":"ref19","first-page":"97","article-title":"Advancing hardware security using polymorphic and stochastic spin-hall effect devices","author":"s p","year":"2018","journal-title":"2018 Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref4","article-title":"Functional analysis attacks on logic locking","author":"d s","year":"2019","journal-title":"2019 Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942150"},{"key":"ref6","first-page":"175","article-title":"CAS-Lock: A security-corruptibility trade-off resilient logic locking scheme","author":"shakya","year":"2020","journal-title":"IACR Transactions on Cryptographic Hardware and Embedded Systems"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2019.2904838"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3299874.3319496"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2019.i1.97-122"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2015.7140252"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2511144"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2020.2991134"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2015.7338407"}],"event":{"name":"2021 58th ACM\/IEEE Design Automation Conference (DAC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2021,12,5]]},"end":{"date-parts":[[2021,12,9]]}},"container-title":["2021 58th ACM\/IEEE Design Automation Conference (DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9585997\/9586083\/09586242.pdf?arnumber=9586242","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T16:55:50Z","timestamp":1652201750000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9586242\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,12,5]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/dac18074.2021.9586242","relation":{},"subject":[],"published":{"date-parts":[[2021,12,5]]}}}