{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,16]],"date-time":"2026-04-16T02:01:34Z","timestamp":1776304894104,"version":"3.50.1"},"reference-count":21,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,12,5]],"date-time":"2021-12-05T00:00:00Z","timestamp":1638662400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,12,5]],"date-time":"2021-12-05T00:00:00Z","timestamp":1638662400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,12,5]],"date-time":"2021-12-05T00:00:00Z","timestamp":1638662400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100003711","name":"Ministry of Science and Technology","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003711","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,12,5]]},"DOI":"10.1109\/dac18074.2021.9586331","type":"proceedings-article","created":{"date-parts":[[2021,11,8]],"date-time":"2021-11-08T23:30:34Z","timestamp":1636414234000},"page":"877-882","source":"Crossref","is-referenced-by-count":16,"title":["Deep Integration of Circuit Simulator and SAT Solver"],"prefix":"10.1109","author":[{"given":"He-Teng","family":"Zhang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jie-Hong R.","family":"Jiang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luca","family":"Amaru","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alan","family":"Mishchenko","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Robert","family":"Brayton","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382542"},{"key":"ref11","first-page":"892","article-title":"A circuit SAT solver with signal correlation guided learning","author":"lu","year":"0","journal-title":"Proc DATE &#x2018;03"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.55"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/43.644605"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.860955"},{"key":"ref15","article-title":"A toolbox for counter-example analysis and optimization","author":"mishchenko","year":"0","journal-title":"Proc IWLS'13"},{"key":"ref16","first-page":"836","article-title":"Improvements to combinational equivalence checking","author":"mishchenko","year":"0","journal-title":"Proc of ICCAD '06"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-40922-X_23"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317905"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364479"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882484"},{"key":"ref3","article-title":"Berkeley Logic Synthesis and Verification Group","year":"0","journal-title":"ABC A System for Sequential Synthesis and Verification"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-18275-4_7"},{"key":"ref5","first-page":"502","article-title":"An extensible SAT-solver","author":"een","year":"2919","journal-title":"Proc SAT&#x2019;03 LNCS"},{"key":"ref8","article-title":"Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver","author":"ganai","year":"0","journal-title":"Proc DAC&#x2019;02"},{"key":"ref7","article-title":"On-the-fly compression of logical circuits","author":"ganay","year":"0","journal-title":"Proc IWLS&#x2019;00"},{"key":"ref2","volume":"3 0","author":"audemard","year":"2013","journal-title":"Glucose sat solver"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218691"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.804386"},{"key":"ref20","year":"0","journal-title":"IWLS 2005 Benchmarks"},{"key":"ref21","year":"0","journal-title":"HWMCC 2015 benchmarks"}],"event":{"name":"2021 58th ACM\/IEEE Design Automation Conference (DAC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2021,12,5]]},"end":{"date-parts":[[2021,12,9]]}},"container-title":["2021 58th ACM\/IEEE Design Automation Conference (DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9585997\/9586083\/09586331.pdf?arnumber=9586331","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T16:55:54Z","timestamp":1652201754000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9586331\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,12,5]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/dac18074.2021.9586331","relation":{},"subject":[],"published":{"date-parts":[[2021,12,5]]}}}