{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T01:43:22Z","timestamp":1740102202628,"version":"3.37.3"},"reference-count":21,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,7,9]],"date-time":"2023-07-09T00:00:00Z","timestamp":1688860800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,7,9]],"date-time":"2023-07-09T00:00:00Z","timestamp":1688860800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,7,9]]},"DOI":"10.1109\/dac56929.2023.10247667","type":"proceedings-article","created":{"date-parts":[[2023,9,15]],"date-time":"2023-09-15T17:31:31Z","timestamp":1694799091000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Algorithms and Hardware for Efficient Processing of Logic-based Neural Networks"],"prefix":"10.1109","author":[{"given":"Jingkai","family":"Hong","sequence":"first","affiliation":[{"name":"University of Southern California,Department of Electrical & Computer Engineering,Los Angeles,CA,USA"}]},{"given":"Arash","family":"Fayyazi","sequence":"additional","affiliation":[{"name":"University of Southern California,Department of Electrical & Computer Engineering,Los Angeles,CA,USA"}]},{"given":"Amirhossein","family":"Esmaili","sequence":"additional","affiliation":[{"name":"University of Southern California,Department of Electrical & Computer Engineering,Los Angeles,CA,USA"}]},{"given":"Mahdi","family":"Nazemi","sequence":"additional","affiliation":[{"name":"University of Southern California,Department of Electrical & Computer Engineering,Los Angeles,CA,USA"}]},{"given":"Massoud","family":"Pedram","sequence":"additional","affiliation":[{"name":"University of Southern California,Department of Electrical & Computer Engineering,Los Angeles,CA,USA"}]}],"member":"263","reference":[{"key":"ref13","article-title":"Very deep convolutional networks for large-scale image recognition","author":"simonyan","year":"2015","journal-title":"ICLRE"},{"key":"ref12","article-title":"Efficient compilation and mapping of fixed function combinational logic onto digital signal processors targeting neural network inference and utilizing high-level synthesis","author":"shahsavani","year":"2022","journal-title":"ACM Trans Reconfigurable Technol Syst"},{"key":"ref15","article-title":"MLP-Mixer: An all-mlp architecture for vision","author":"tolstikhin","year":"2021","journal-title":"34 NeurIPS"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375321"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/12.83662"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM51124.2021.00053"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3287722"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.5244\/C.30.87"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS51556.2021.9401214"},{"key":"ref1","article-title":"On the RTL implementation of FINN matrix vector compute unit","volume":"abs 2201 11409","author":"alam","year":"2022","journal-title":"CoRR"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/FPL50879.2020.00055"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021744"},{"article-title":"Yosys open synthesis suite","year":"2016","author":"wolf","key":"ref19"},{"key":"ref18","article-title":"Attention is all you need","volume":"abs 1706 3762","author":"vaswani","year":"2017","journal-title":"CoRR"},{"key":"ref8","article-title":"Automatic heterogeneous quantization of deep neural networks for low-latency inference on the edge for particle detectors","author":"c","year":"2021","journal-title":"Nat Mach Intell"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2017.243"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DSD53832.2021.00023"},{"key":"ref4","article-title":"BERT: pre-training of deep bidirectional transformers for language understanding","author":"devlin","year":"2019","journal-title":"HLT-NAACL The Association for Computational Linguistics"},{"key":"ref3","article-title":"ABC: an academic industrial-strength verification tool","volume":"6174","author":"brayton","year":"2010","journal-title":"CAV"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1162\/neco.1997.9.8.1735"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1088\/1748-0221\/13\/07\/P07027"}],"event":{"name":"2023 60th ACM\/IEEE Design Automation Conference (DAC)","start":{"date-parts":[[2023,7,9]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2023,7,13]]}},"container-title":["2023 60th ACM\/IEEE Design Automation Conference (DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10247654\/10247655\/10247667.pdf?arnumber=10247667","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,2]],"date-time":"2023-10-02T17:41:49Z","timestamp":1696268509000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10247667\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,7,9]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/dac56929.2023.10247667","relation":{},"subject":[],"published":{"date-parts":[[2023,7,9]]}}}