{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,17]],"date-time":"2025-09-17T16:00:18Z","timestamp":1758124818123},"reference-count":18,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,7,9]],"date-time":"2023-07-09T00:00:00Z","timestamp":1688860800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,7,9]],"date-time":"2023-07-09T00:00:00Z","timestamp":1688860800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,7,9]]},"DOI":"10.1109\/dac56929.2023.10247791","type":"proceedings-article","created":{"date-parts":[[2023,9,15]],"date-time":"2023-09-15T17:31:31Z","timestamp":1694799091000},"page":"1-6","source":"Crossref","is-referenced-by-count":7,"title":["A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware"],"prefix":"10.1109","author":[{"given":"Yanchi","family":"Dong","sequence":"first","affiliation":[{"name":"Peking University,Beijing,China"}]},{"given":"Tianyu","family":"Jia","sequence":"additional","affiliation":[{"name":"Peking University,Beijing,China"}]},{"given":"Kaixuan","family":"Du","sequence":"additional","affiliation":[{"name":"Peking University,Beijing,China"}]},{"given":"Yiqi","family":"Jing","sequence":"additional","affiliation":[{"name":"Peking University,Beijing,China"}]},{"given":"Qijun","family":"Wang","sequence":"additional","affiliation":[{"name":"Nano Core Chip Electronic Technology,Hangzhou,China"}]},{"given":"Pixian","family":"Zhan","sequence":"additional","affiliation":[{"name":"Nano Core Chip Electronic Technology,Hangzhou,China"}]},{"given":"Yadong","family":"Zhang","sequence":"additional","affiliation":[{"name":"Nano Core Chip Electronic Technology,Hangzhou,China"}]},{"given":"Fengyun","family":"Yan","sequence":"additional","affiliation":[{"name":"Nano Core Chip Electronic Technology,Hangzhou,China"}]},{"given":"Yufei","family":"Ma","sequence":"additional","affiliation":[{"name":"Peking University,Beijing,China"}]},{"given":"Yun","family":"Liang","sequence":"additional","affiliation":[{"name":"Peking University,Beijing,China"}]},{"given":"Le","family":"Ye","sequence":"additional","affiliation":[{"name":"Peking University,Beijing,China"}]},{"given":"Ru","family":"Huang","sequence":"additional","affiliation":[{"name":"Peking University,Beijing,China"}]}],"member":"263","reference":[{"key":"ref13","article-title":"Simba: Scaling deep-learning inference with multi-chip-module-based architecture","author":"shao","year":"2019","journal-title":"IEEE Micro"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3029097"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942149"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2019.00042"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731716"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731757"},{"key":"ref2","article-title":"MicroNets: neural network architectures for deploying TinyML applications on commodity microcontrollers","author":"banbury","year":"2021","journal-title":"MLSys"},{"key":"ref1","article-title":"MCUNet: tiny deep learning on IoT devices","author":"lin","year":"2020","journal-title":"NeurIPS"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.23919\/DATE54114.2022.9774747"},{"key":"ref16","article-title":"Sparseloop: an analytical approach to sparse tensor accelerator modeling","author":"wu","year":"2022","journal-title":"IEEE Micro"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2297402"},{"article-title":"CFU playground: full-stack open-source framework for tiny machine learning (tinyML) acceleration on FPGAs","year":"2022","author":"prakash","key":"ref8"},{"key":"ref7","article-title":"NCPU: An embedded neural CPU architecture on resource-constrained low power devices for real-time end-to-end performance","author":"jia","year":"2020","journal-title":"IEEE Micro"},{"key":"ref9","article-title":"A technical overview of Cortex-M55 and Ethos-U55","author":"skillman","year":"2020","journal-title":"IEEE Hot Chips Symposium"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586216"},{"key":"ref3","article-title":"MLPerf Tiny Benchmark","author":"banbury","year":"2021","journal-title":"NeurIPS Track on Datasets and Benchmarks"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS51385.2021.00027"},{"key":"ref5","article-title":"The larger the fairer? small neural networks can achieve fairness for edge devices","author":"sheng","year":"2022","journal-title":"IEEE DAC"}],"event":{"name":"2023 60th ACM\/IEEE Design Automation Conference (DAC)","start":{"date-parts":[[2023,7,9]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2023,7,13]]}},"container-title":["2023 60th ACM\/IEEE Design Automation Conference (DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10247654\/10247655\/10247791.pdf?arnumber=10247791","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,2]],"date-time":"2023-10-02T17:41:20Z","timestamp":1696268480000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10247791\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,7,9]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/dac56929.2023.10247791","relation":{},"subject":[],"published":{"date-parts":[[2023,7,9]]}}}