{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,11]],"date-time":"2026-07-11T22:05:41Z","timestamp":1783807541350,"version":"3.55.0"},"reference-count":41,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,6,22]],"date-time":"2025-06-22T00:00:00Z","timestamp":1750550400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,6,22]],"date-time":"2025-06-22T00:00:00Z","timestamp":1750550400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,6,22]]},"DOI":"10.1109\/dac63849.2025.11132417","type":"proceedings-article","created":{"date-parts":[[2025,9,15]],"date-time":"2025-09-15T17:35:41Z","timestamp":1757957741000},"page":"1-7","source":"Crossref","is-referenced-by-count":2,"title":["MemSeer: Leverage Memory Failure Distinctions and Multi-Grained Prediction in Ultra-Scale Heterogeneous X86\/ARM Clusters"],"prefix":"10.1109","author":[{"given":"Yunfei","family":"Gu","sequence":"first","affiliation":[{"name":"Shanghai Jiao Tong University,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yixuan","family":"Liu","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xinyuan","family":"Wu","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Bo","family":"Shao","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chentao","family":"Wu","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shiyi","family":"Li","sequence":"additional","affiliation":[{"name":"Harbin Institute of Technology,Shenzhen,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jieru","family":"Zhao","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jie","family":"Li","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Minyi","family":"Guo","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kunlin","family":"Yang","sequence":"additional","affiliation":[{"name":"Huawei Technologies Co., Ltd.,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Wengui","family":"Zhang","sequence":"additional","affiliation":[{"name":"Huawei Technologies Co., Ltd.,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Feilong","family":"Lin","sequence":"additional","affiliation":[{"name":"Huawei Technologies Co., Ltd.,China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00019"},{"key":"ref2","volume-title":"Service level agreement in cloud computing","author":"Patel","year":"2009"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ITherm45881.2020.9190253"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2007.40"},{"key":"ref5","volume-title":"Intel\u00ae e7500 chipset mch intel\u00ae x4 single device data correction (x4 sddc) implementation and validation","author":"Note","year":"2002"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2503210.2503243"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2014.50"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/CLUSTER.2012.68"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2017.2779151"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4842-4932-1_17"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3154448.3154451"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830804"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/SC41405.2020.00065"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3488423.3519316"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3357526.3357527"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD53106.2021.00077"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/COMST.2018.2794881"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3240302.3240309"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/EDCC51268.2020.00016"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JCC53141.2021.00012"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/SRDS55811.2022.00032"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/BigData55660.2022.10020671"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC47752.2019.9041963"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/VTS50974.2021.9441059"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/SC41404.2022.00081"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/DSN58367.2023.00031"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/DSN53405.2022.00037"},{"key":"ref28","doi-asserted-by":"crossref","DOI":"10.1109\/DSN-S60304.2024.00033","volume-title":"Investigating memory failure prediction across cpu architectures","author":"Yu","year":"2024"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/3124680.3124742"},{"key":"ref30","article-title":"Memory errors and dell emc poweredge yx4x server memory ras features","volume-title":"Tech. Rep.","author":"Technologies","year":"2020"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2014.7001366"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/2939672.2939785"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.17849\/insm-47-01-31\u201339.1"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.5555\/3294996.3295070"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1016\/j.neucom.2020.01.006"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2015.7178838"},{"issue":"64-67","key":"ref37","first-page":"2","article-title":"Recurrent neural networks","volume":"5","author":"Medsker","year":"2001","journal-title":"Design and Applications"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/2492101.1555372"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2014.63"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/2248487.2150989"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.57"}],"event":{"name":"2025 62nd ACM\/IEEE Design Automation Conference (DAC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2025,6,22]]},"end":{"date-parts":[[2025,6,25]]}},"container-title":["2025 62nd ACM\/IEEE Design Automation Conference (DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11132383\/11132091\/11132417.pdf?arnumber=11132417","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,16]],"date-time":"2025-09-16T05:43:33Z","timestamp":1758001413000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11132417\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,6,22]]},"references-count":41,"URL":"https:\/\/doi.org\/10.1109\/dac63849.2025.11132417","relation":{},"subject":[],"published":{"date-parts":[[2025,6,22]]}}}