{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,17]],"date-time":"2025-09-17T06:12:27Z","timestamp":1758089547467,"version":"3.44.0"},"reference-count":31,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,6,22]],"date-time":"2025-06-22T00:00:00Z","timestamp":1750550400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,6,22]],"date-time":"2025-06-22T00:00:00Z","timestamp":1750550400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,6,22]]},"DOI":"10.1109\/dac63849.2025.11132950","type":"proceedings-article","created":{"date-parts":[[2025,9,15]],"date-time":"2025-09-15T17:35:41Z","timestamp":1757957741000},"page":"1-7","source":"Crossref","is-referenced-by-count":0,"title":["333-eDRAM - 3T Embedded DRAM Leveraging Monolithic 3D Integration of 3 Transistor Types: IGZO, Carbon Nanotube and Silicon FETs"],"prefix":"10.1109","author":[{"given":"David","family":"Kong","sequence":"first","affiliation":[{"name":"Harvard University,MA,USA"}]},{"given":"Shvetank","family":"Prakash","sequence":"additional","affiliation":[{"name":"Harvard University,MA,USA"}]},{"given":"Jedrzej","family":"Kufel","sequence":"additional","affiliation":[{"name":"Pragmatic Semiconductor,Cambridge,UK"}]},{"given":"Georgios","family":"Kyriazidis","sequence":"additional","affiliation":[{"name":"Harvard University,MA,USA"}]},{"given":"Yasmine","family":"Omri","sequence":"additional","affiliation":[{"name":"Harvard University,MA,USA"}]},{"given":"David","family":"Verity","sequence":"additional","affiliation":[{"name":"Pragmatic Semiconductor,Cambridge,UK"}]},{"given":"Emre","family":"Ozer","sequence":"additional","affiliation":[{"name":"Pragmatic Semiconductor,Cambridge,UK"}]},{"given":"Vijay Janapa","family":"Reddi","sequence":"additional","affiliation":[{"name":"Harvard University,MA,USA"}]},{"given":"Gage","family":"Hills","sequence":"additional","affiliation":[{"name":"Harvard University,MA,USA"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2018.2882603"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA57654.2024.00058"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2022.3144461"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2541228.2541231"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-019-1493-8"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1038\/s41699-023-00371-7"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2024.3372937"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-024-07976-y"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.32388\/tl92ja"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2010.5556234"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46769.2022.9830448"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-018-0106-0"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/s42341-024-00536-1"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2016.04.006"},{"year":"2021","key":"ref15","article-title":"Embench text TM: Open Benchmarks for Embedded Platforms"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1063\/1.1697872"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2457453"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2457424"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2009.2024022"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnology18217.2020.9265052"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM13553.2020.9371900"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/iedm19574.2021.9720596"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM45741.2023.10413772"},{"key":"ref24","first-page":"1","article-title":"First demonstration of sub-12 nm L_g gate last IGZO-TFTs with oxygen tunnel architecture for front gate devices","volume-title":"2021 Symposium on VLSI Technology","author":"Subhechha"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2018.2871841"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2014.7047164"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM13553.2020.9371899"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522314"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00037"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2014.2360527"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/3321693"}],"event":{"name":"2025 62nd ACM\/IEEE Design Automation Conference (DAC)","start":{"date-parts":[[2025,6,22]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2025,6,25]]}},"container-title":["2025 62nd ACM\/IEEE Design Automation Conference (DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11132383\/11132091\/11132950.pdf?arnumber=11132950","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,16]],"date-time":"2025-09-16T05:49:59Z","timestamp":1758001799000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11132950\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,6,22]]},"references-count":31,"URL":"https:\/\/doi.org\/10.1109\/dac63849.2025.11132950","relation":{},"subject":[],"published":{"date-parts":[[2025,6,22]]}}}