{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,17]],"date-time":"2025-09-17T06:11:04Z","timestamp":1758089464905,"version":"3.44.0"},"reference-count":54,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,6,22]],"date-time":"2025-06-22T00:00:00Z","timestamp":1750550400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,6,22]],"date-time":"2025-06-22T00:00:00Z","timestamp":1750550400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,6,22]]},"DOI":"10.1109\/dac63849.2025.11133076","type":"proceedings-article","created":{"date-parts":[[2025,9,15]],"date-time":"2025-09-15T17:35:41Z","timestamp":1757957741000},"page":"1-7","source":"Crossref","is-referenced-by-count":0,"title":["VISTA: Optimizing GPU Scheduling through Versatile Locality-Aware Data Sharing"],"prefix":"10.1109","author":[{"given":"Hajar","family":"Falahati","sequence":"first","affiliation":[{"name":"Barcelona Supercomputing Center (BSC),Barcelona,Spain"}]},{"given":"Negin","family":"Mahani","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center (BSC),Barcelona,Spain"}]},{"given":"Adrian","family":"Cristal","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center (BSC),Barcelona,Spain"}]},{"given":"Osman","family":"Unsal","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center (BSC),Barcelona,Spain"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3001589"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3419973"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3653019"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3291606"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2015.23"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-014-1331-6"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/CADS.2013.6714230"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.16"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2017.2693371"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2017.106"},{"key":"ref11","article-title":"Improving GPU performance via large warps and twolevel warp scheduling","author":"Narasiman","year":"2011","journal-title":"MICRO"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.38"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2964791.2901468"},{"key":"ref14","article-title":"Neither More nor Less: Optimizing Thread-level Parallelism for GPGPUs","author":"Kayiran","year":"2013","journal-title":"PACT"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/micro.2012.16"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056031"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2499368.2451158"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056024"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2024723.2000093"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/micro.2014.16"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2019.00061"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2018.00108"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001199"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2024.3371062"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2018.2873679"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2014.0092"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/3429981"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2022.3154315"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919648"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2012.6402918"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/InPar.2012.6339595"},{"key":"ref33","article-title":"Parboil: A revised benchmark suite for scientific and commercial throughput computing","author":"Stratton","year":"2012","journal-title":"Center for Reliable and High-Performance Computing"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2013.6704684"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2014.6983053"},{"year":"2009","key":"ref36","article-title":"Cuda sdk 2.3"},{"year":"2017","key":"ref37","article-title":"Deepbench"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358319"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/3613424.3623782"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA56546.2023.10070957"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00047"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480063"},{"year":"2017","key":"ref43","article-title":"Volta architecture whitepaper"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/4.509850"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/3508036"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056023"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/2159430.2159443"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1145\/3140659.3080239"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2021.3096191"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-01766-7"},{"key":"ref51","article-title":"Learning memory access patterns","author":"Hashemi","year":"2018","journal-title":"PMLR"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322207"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00033"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2022.12.004"}],"event":{"name":"2025 62nd ACM\/IEEE Design Automation Conference (DAC)","start":{"date-parts":[[2025,6,22]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2025,6,25]]}},"container-title":["2025 62nd ACM\/IEEE Design Automation Conference (DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11132383\/11132091\/11133076.pdf?arnumber=11133076","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,16]],"date-time":"2025-09-16T05:24:53Z","timestamp":1758000293000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11133076\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,6,22]]},"references-count":54,"URL":"https:\/\/doi.org\/10.1109\/dac63849.2025.11133076","relation":{},"subject":[],"published":{"date-parts":[[2025,6,22]]}}}