{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,11,7]],"date-time":"2026-11-07T03:30:11Z","timestamp":1794022211108,"version":"4.8.0"},"reference-count":22,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,6,22]],"date-time":"2025-06-22T00:00:00Z","timestamp":1750550400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,6,22]],"date-time":"2025-06-22T00:00:00Z","timestamp":1750550400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,6,22]]},"DOI":"10.1109\/dac63849.2025.11133142","type":"proceedings-article","created":{"date-parts":[[2025,9,15]],"date-time":"2025-09-15T17:35:41Z","timestamp":1757957741000},"page":"1-7","source":"Crossref","is-referenced-by-count":5,"title":["GSIM: Accelerating RTL Simulation for Large-Scale Designs"],"prefix":"10.1109","author":[{"given":"Lu","family":"Chen","sequence":"first","affiliation":[{"name":"Institute of Computing Technology, Chinese Academy of Sciences,State Key Lab of Processors,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Dingyi","family":"Zhao","sequence":"additional","affiliation":[{"name":"Beijing Institute of Open Source Chip,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zihao","family":"Yu","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology, Chinese Academy of Sciences,State Key Lab of Processors,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ninghui","family":"Sun","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology, Chinese Academy of Sciences,State Key Lab of Processors,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yungang","family":"Bao","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology, Chinese Academy of Sciences,State Key Lab of Processors,China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3582016.3582034"},{"key":"ref2","first-page":"180","article-title":"Khronos: Fusing memory access for improved hardware rtl simulation","volume-title":"2023 56th IEEE\/ACM International Symposium on Microarchitecture (MICRO)","author":"Zhou"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218632"},{"key":"ref4","doi-asserted-by":"crossref","DOI":"10.1201\/b19569","article-title":"Electronic Design Automation for IC System Design, Verification, and Testing","author":"Lavagno","year":"2017"},{"key":"ref5","article-title":"Verilator","author":"Snyder"},{"key":"ref6","volume-title":"The rocket chip generator","author":"Asanovi\u0107","year":"2016"},{"key":"ref7","volume-title":"The berkeley out-of-order machine (boom): An industry-competitive, synthesizable, parameterized risc-v processor","author":"Celio","year":"2015"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00080"},{"key":"ref9","article-title":"Coremark"},{"key":"ref10","article-title":"Arcilator: Fast and cycle-accurate hardware simulation in circt","author":"Martin Erhart"},{"key":"ref11","volume-title":"Electronic design automation: synthesis, verification, and test","author":"Wang","year":"2009"},{"key":"ref12","article-title":"Vcs: Functional verification solution"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3622781.3674184"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/321623.321627"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203780"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/CGO51591.2021.9370308"},{"key":"ref17","article-title":"Circt: Circuit ir compilers and tools"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228584"},{"key":"ref19","article-title":"Gem5: Checkpoints"},{"key":"ref20","article-title":"Spec cpu\u00ae 2006"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/605432.605403"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250713"}],"event":{"name":"2025 62nd ACM\/IEEE Design Automation Conference (DAC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2025,6,22]]},"end":{"date-parts":[[2025,6,25]]}},"container-title":["2025 62nd ACM\/IEEE Design Automation Conference (DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11132383\/11132091\/11133142.pdf?arnumber=11133142","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,16]],"date-time":"2025-09-16T05:39:26Z","timestamp":1758001166000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11133142\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,6,22]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/dac63849.2025.11133142","relation":{},"subject":[],"published":{"date-parts":[[2025,6,22]]}}}