{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T16:03:07Z","timestamp":1780675387006,"version":"3.54.1"},"reference-count":37,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,6,22]],"date-time":"2025-06-22T00:00:00Z","timestamp":1750550400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,6,22]],"date-time":"2025-06-22T00:00:00Z","timestamp":1750550400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,6,22]]},"DOI":"10.1109\/dac63849.2025.11133160","type":"proceedings-article","created":{"date-parts":[[2025,9,15]],"date-time":"2025-09-15T17:35:41Z","timestamp":1757957741000},"page":"1-7","source":"Crossref","is-referenced-by-count":1,"title":["A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis"],"prefix":"10.1109","author":[{"given":"Xun","family":"Jiang","sequence":"first","affiliation":[{"name":"Peking University,School of IC"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Haoran","family":"Lu","sequence":"additional","affiliation":[{"name":"Peking University,School of IC"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yuxuan","family":"Zhao","sequence":"additional","affiliation":[{"name":"The Chinese University of Hong Kong,Department of CSE"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jiarui","family":"Wang","sequence":"additional","affiliation":[{"name":"Peking University,School of IC"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zizheng","family":"Guo","sequence":"additional","affiliation":[{"name":"Peking University,School of IC"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Heng","family":"Wu","sequence":"additional","affiliation":[{"name":"Peking University,School of IC"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Bei","family":"Yu","sequence":"additional","affiliation":[{"name":"The Chinese University of Hong Kong,Department of CSE"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sung Kyu","family":"Lim","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology,School of ECE"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Runsheng","family":"Wang","sequence":"additional","affiliation":[{"name":"Peking University,School of IC"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ru","family":"Huang","sequence":"additional","affiliation":[{"name":"Peking University,School of IC"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yibo","family":"Lin","sequence":"additional","affiliation":[{"name":"Peking University,School of IC"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/iedm19574.2021.9720528"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM45741.2023.10413867"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993617"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC58780.2024.10473897"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3649476.3658728"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3649329.3657333"},{"key":"ref7","volume-title":"A methodology for back-side clock delivery network design compatible with commercial eda flows","author":"Bethur","year":"2023"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/jproc.2018.2882603"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46783.2024.10631460"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.23919\/VLSITechnologyandCir57934.2023.10185369"},{"key":"ref11","article-title":"Tsmc a16 technology"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3386263.3406949"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.1992.270316"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/157485.165066"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3649329.3658243"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1990.112223"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2889756"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837295"},{"key":"ref19","first-page":"86","article-title":"Clock tree synthesis under aggressive buffer insertion","volume-title":"Proceedings of the 47th Design Automation Conference","author":"Chen"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1996.545606"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2010.5450402"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3287681"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/s11390-015-1531-4"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1997.628871"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/SLIP.2015.7171709"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/2003695.2003708"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2011.5722264"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2019.8824801"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46783.2024.10631379"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372664"},{"key":"ref31","article-title":"Multi objective optimization: concepts and methods for engineering","author":"Marler","year":"2009"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2016.04.006"},{"key":"ref33","article-title":"Openroad"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2539926"},{"key":"ref35","article-title":"Cadence Innovus Implementation System"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062184"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942120"}],"event":{"name":"2025 62nd ACM\/IEEE Design Automation Conference (DAC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2025,6,22]]},"end":{"date-parts":[[2025,6,25]]}},"container-title":["2025 62nd ACM\/IEEE Design Automation Conference (DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11132383\/11132091\/11133160.pdf?arnumber=11133160","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,16]],"date-time":"2025-09-16T05:39:30Z","timestamp":1758001170000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11133160\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,6,22]]},"references-count":37,"URL":"https:\/\/doi.org\/10.1109\/dac63849.2025.11133160","relation":{},"subject":[],"published":{"date-parts":[[2025,6,22]]}}}