{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T10:49:14Z","timestamp":1725619754567},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,11]]},"DOI":"10.1109\/dasip.2011.6136852","type":"proceedings-article","created":{"date-parts":[[2012,1,31]],"date-time":"2012-01-31T11:39:34Z","timestamp":1328009974000},"page":"1-7","source":"Crossref","is-referenced-by-count":6,"title":["Fast and accurate hybrid power estimation methodology for embedded systems"],"prefix":"10.1109","author":[{"given":"Santhosh Kumar","family":"Rethinagiri","sequence":"first","affiliation":[]},{"given":"Rabie","family":"Ben Atitallah","sequence":"additional","affiliation":[]},{"given":"Smail","family":"Niar","sequence":"additional","affiliation":[]},{"given":"Eric","family":"Senn","sequence":"additional","affiliation":[]},{"given":"Jean-Luc","family":"Dekeyser","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1118299.1118431"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1084834.1084874"},{"year":"0","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605403"},{"journal-title":"The SoCLib Project An Open Modelling and Simulation Platform for System on Chip Design","year":"2009","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/s10617-010-9064-0"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/92.335012"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337436"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1166\/jolpe.2009.1041"},{"journal-title":"Transaction-level modeling for architectural and power analysis of powerpc and coreconnect-based systems","year":"0","author":"dhanwada","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2007.363739"},{"year":"2010","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268921"},{"key":"ref7","first-page":"15","article-title":"Softexplorer: estimation, characterization and optimization of the power and energy consumption at the algorithmic level","author":"laurent","year":"2004","journal-title":"Fourteenth International Workshop on Power and Timing Modeling (PATMOS 2004)"},{"key":"ref2","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref9","first-page":"311","article-title":"High level energy estimation for DSP systems","author":"laurent","year":"2001","journal-title":"Int'l Workshop on Power and Timing Modeling Optimization and Simulation PATMOS"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2030268"}],"event":{"name":"2011 Conference on Design and Architectures for Signal and Image Processing (DASIP)","start":{"date-parts":[[2011,11,2]]},"location":"Tampere, Finland","end":{"date-parts":[[2011,11,4]]}},"container-title":["Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6111682\/6136840\/06136852.pdf?arnumber=6136852","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T10:32:14Z","timestamp":1490092334000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6136852\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,11]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/dasip.2011.6136852","relation":{},"subject":[],"published":{"date-parts":[[2011,11]]}}}