{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T19:20:43Z","timestamp":1729624843747,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,11]]},"DOI":"10.1109\/dasip.2011.6136883","type":"proceedings-article","created":{"date-parts":[[2012,1,31]],"date-time":"2012-01-31T16:39:34Z","timestamp":1328027974000},"page":"1-6","source":"Crossref","is-referenced-by-count":2,"title":["Power consumption improvement with residue code for fault tolerance on SRAM FPGA"],"prefix":"10.1109","author":[{"given":"Amiel","family":"Frederic","sequence":"first","affiliation":[]},{"given":"Ea","family":"Thomas","sequence":"additional","affiliation":[]},{"given":"Vinay","family":"Vashishtha","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"(Cyclone IV Device Handbook Vall) ALTERA","article-title":"SEU mitigation in Cyclone IV Devices","year":"0","key":"ref4"},{"journal-title":"Radiation effect in FPGAs Actel","year":"0","author":"wang","key":"ref3"},{"key":"ref10","article-title":"Impact of different power reduction techniques at architectural level on modern FPGAs","author":"blasinski","year":"2010","journal-title":"LASCAS"},{"key":"ref6","first-page":"32","author":"lima kastensmidt","year":"0","journal-title":"Fault-Tolerance Techniques for SRAM-based FPGAs"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2007.910871"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1147\/rd.62.0200"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/4.281"},{"key":"ref7","doi-asserted-by":"crossref","DOI":"10.1145\/775832.775997","article-title":"Designing Fault Tolerant Systems into SRAM-based FPGAs","author":"lima","year":"2003","journal-title":"DAC"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/23.556861"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"1322","DOI":"10.1109\/T-C.1971.223134","article-title":"arithmetic error codes: cost and effectiveness studies for application in digital system design","volume":"c 20","author":"avizienis","year":"1971","journal-title":"IEEE Transactions on Computers"},{"journal-title":"wp-01059-stratix-iv-40nm-power - Altera white paper","year":"0","key":"ref1"}],"event":{"name":"2011 Conference on Design and Architectures for Signal and Image Processing (DASIP)","start":{"date-parts":[[2011,11,2]]},"location":"Tampere, Finland","end":{"date-parts":[[2011,11,4]]}},"container-title":["Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6111682\/6136840\/06136883.pdf?arnumber=6136883","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,6,14]],"date-time":"2023-06-14T05:37:40Z","timestamp":1686721060000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6136883\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,11]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/dasip.2011.6136883","relation":{},"subject":[],"published":{"date-parts":[[2011,11]]}}}