{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T06:34:28Z","timestamp":1729665268996,"version":"3.28.0"},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,11]]},"DOI":"10.1109\/dasip.2011.6136890","type":"proceedings-article","created":{"date-parts":[[2012,1,31]],"date-time":"2012-01-31T16:39:34Z","timestamp":1328027974000},"page":"1-8","source":"Crossref","is-referenced-by-count":5,"title":["FeRoNoC: Flexible and extensible Router implementation for diagonal mesh topology"],"prefix":"10.1109","author":[{"given":"Majdi","family":"Elhajji","sequence":"first","affiliation":[]},{"given":"Brahim","family":"Attia","sequence":"additional","affiliation":[]},{"given":"Abdelkrim","family":"Zitouni","sequence":"additional","affiliation":[]},{"given":"Rached","family":"Tourki","sequence":"additional","affiliation":[]},{"given":"Samy","family":"Meftali","sequence":"additional","affiliation":[]},{"given":"Jean-luc","family":"Dekeyser","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.99"},{"key":"ref11","first-page":"553","article-title":"Exact analysis of hot-potato routing","volume":"192","author":"uriel","year":"0","journal-title":"33rd Ann Symp Foundations of Computer Science"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"69","DOI":"10.1016\/j.vlsi.2004.03.003","article-title":"Hermes: an infrastructure for low area overhead packet-switching networks on chip","volume":"38","author":"goossens","year":"2004","journal-title":"VLSI Journal"},{"key":"ref13","article-title":"Deadlock-free message routing in multiprocesor interconnection networks","author":"dally","year":"0","journal-title":"IEEE Trans- actions"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"1025","DOI":"10.1109\/TC.2005.134","article-title":"Performance evaluation and design trade-offs for network-on-chip interconnect architectures","volume":"54","author":"partha","year":"2005","journal-title":"IEEE Transaction on Computers"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.243841"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20045016"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2007.4380772"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2006.55"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"70","DOI":"10.1109\/2.976921","article-title":"Networks on chips: A new soc paradigm","volume":"35","author":"luca","year":"2002","journal-title":"IEEE Computer"},{"key":"ref3","first-page":"105","article-title":"Powering networks on chips energy-efficient and reliable interconnect design for socs","author":"luca","year":"2002","journal-title":"ISSS'OI ACM"},{"journal-title":"Design of Cost-Efficient Interconnect Processing Units Spidergon STNoC","year":"2008","author":"marcello","key":"ref6"},{"key":"ref5","first-page":"250","article-title":"Agenetic architecture for on-chip packet-switched interconections","author":"pierre","year":"2000","journal-title":"Design Automation and Test in Europe IEEE"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.830919"},{"journal-title":"A generic network on chip model","year":"2009","author":"schmaltz","key":"ref7"},{"key":"ref2","first-page":"105","article-title":"The nostrum backbone communication protocol stack for networks on chip","author":"mikael","year":"2004","journal-title":"VLSI Design IEEE"},{"key":"ref1","first-page":"105","article-title":"A network on chip architecture and design methodology","author":"shashi","year":"2002","journal-title":"IEEE computer Society Annual Symposium IEEE"},{"key":"ref9","article-title":"A parametric and scalable network-on-chip","author":"zeferino","year":"2003","journal-title":"IEEE Symposium on Integrated Circuits and Systems Design"}],"event":{"name":"2011 Conference on Design and Architectures for Signal and Image Processing (DASIP)","start":{"date-parts":[[2011,11,2]]},"location":"Tampere, Finland","end":{"date-parts":[[2011,11,4]]}},"container-title":["Proceedings of the 2011 Conference on Design &amp; Architectures for Signal &amp; Image Processing (DASIP)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6111682\/6136840\/06136890.pdf?arnumber=6136890","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T13:35:34Z","timestamp":1497965734000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6136890\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,11]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/dasip.2011.6136890","relation":{},"subject":[],"published":{"date-parts":[[2011,11]]}}}