{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T06:24:16Z","timestamp":1725517456592},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,11]]},"DOI":"10.1109\/dasip.2011.6136899","type":"proceedings-article","created":{"date-parts":[[2012,1,31]],"date-time":"2012-01-31T16:39:34Z","timestamp":1328027974000},"page":"1-8","source":"Crossref","is-referenced-by-count":0,"title":["A framework for the design of reconfigurable fault tolerant architectures"],"prefix":"10.1109","author":[{"given":"Hung Manh","family":"Pham","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sebastien","family":"Pillement","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Olivier","family":"Pasquier","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sebastien","family":"Le Nours","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/OLT.2004.1319668"},{"journal-title":"Xilinx Application Note","article-title":"PPC405 lockstep system on mI310","year":"0","key":"ref3"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICM.2006.373295"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2008.2001422"},{"journal-title":"Xilinx Application Note XAPP138","article-title":"Virtex FPGA Series Configuration and Read-back","year":"2005","key":"ref5"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"284","DOI":"10.1109\/ReConFig.2009.47","article-title":"A fault-tolerant layer for dynamically reconfigurable multiprocessor system-on-chip","author":"pham","year":"2009","journal-title":"International Conference on Reconfigurable Computing and FPGAs (ReConFig)"},{"journal-title":"LightWeight IP","year":"0","key":"ref12"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-00641-8_31"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1404371.1404424"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1404371.1404426"},{"year":"0","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-27776-7_4"}],"event":{"name":"2011 Conference on Design and Architectures for Signal and Image Processing (DASIP)","start":{"date-parts":[[2011,11,2]]},"location":"Tampere, Finland","end":{"date-parts":[[2011,11,4]]}},"container-title":["Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6111682\/6136840\/06136899.pdf?arnumber=6136899","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T13:35:36Z","timestamp":1497965736000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6136899\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,11]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/dasip.2011.6136899","relation":{},"subject":[],"published":{"date-parts":[[2011,11]]}}}