{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T15:01:29Z","timestamp":1761663689615,"version":"3.28.0"},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,9]]},"DOI":"10.1109\/dasip.2017.8122128","type":"proceedings-article","created":{"date-parts":[[2017,11,30]],"date-time":"2017-11-30T21:58:24Z","timestamp":1512079104000},"page":"1-6","source":"Crossref","is-referenced-by-count":5,"title":["Power efficient dataflow design for a heterogeneous smart camera architecture"],"prefix":"10.1109","author":[{"given":"Deepayan","family":"Bhowmik","sequence":"first","affiliation":[]},{"given":"Paulo","family":"Garcia","sequence":"additional","affiliation":[]},{"given":"Andrew","family":"Wallace","sequence":"additional","affiliation":[]},{"given":"Robert","family":"Stewart","sequence":"additional","affiliation":[]},{"given":"Greg","family":"Michaelson","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-015-1044-y"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-49956-7_14"},{"journal-title":"High-Level Synthesis of Dataflow Programs for Heterogeneous Platforms Design Flow Tools and Design Space Exploration","year":"2015","author":"bezati","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TPAMI.2012.89"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2016.2627241"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2011.41"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TII.2014.2319581"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/BF02476026"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISPA.2013.6703837"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TPAMI.2010.70"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-7705-1_3"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-7705-1_1"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TIP.2015.2487048"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2789116.2789145"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1016\/j.inffus.2014.07.002"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TITS.2011.2182610"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"23","DOI":"10.1109\/MC.2014.134","article-title":"Smart camera networks","volume":"47","author":"reisslein","year":"2014","journal-title":"Computer"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2014.01.006"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2502081.2502231"},{"journal-title":"Reducing Power Consumption and Increasing Bandwidth on 28-nm FPGAs","year":"2012","key":"ref20"}],"event":{"name":"2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)","start":{"date-parts":[[2017,9,27]]},"location":"Dresden","end":{"date-parts":[[2017,9,29]]}},"container-title":["2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8114691\/8122106\/08122128.pdf?arnumber=8122128","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,7]],"date-time":"2019-10-07T05:28:30Z","timestamp":1570426110000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8122128\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,9]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/dasip.2017.8122128","relation":{},"subject":[],"published":{"date-parts":[[2017,9]]}}}