{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,24]],"date-time":"2025-06-24T05:44:37Z","timestamp":1750743877697},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1109\/dasip.2018.8597119","type":"proceedings-article","created":{"date-parts":[[2019,1,3]],"date-time":"2019-01-03T18:11:59Z","timestamp":1546539119000},"page":"70-75","source":"Crossref","is-referenced-by-count":2,"title":["The VINEYARD Framework for Heterogeneous Cloud Applications: The BrainFrame Case"],"prefix":"10.1109","author":[{"given":"Harry","family":"Sidiropoulos","sequence":"first","affiliation":[]},{"given":"George","family":"Chatzikonstantis","sequence":"additional","affiliation":[]},{"given":"Dimitrios","family":"Soudris","sequence":"additional","affiliation":[]},{"given":"Christos","family":"Strydis","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-67630-2_27"},{"journal-title":"VINEYARD Aceelerator repository","year":"0","key":"ref3"},{"key":"ref10","article-title":"Intel Xeon Phi Processor High Performance Programming: Knights Landing Edition","author":"jeffers","year":"2016","journal-title":"Morgan Kaufmann"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.23919\/FPL.2017.8056788"},{"journal-title":"a unified analytics engine for large-scale data processing","year":"0","author":"apache","key":"ref11"},{"journal-title":"Intel Open Programmable Acceleration Engine (OPAE)","year":"0","key":"ref5"},{"journal-title":"A simulator-independent language for building neuronal network models","year":"0","key":"ref12"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1088\/1741-2552\/aa7fc5"},{"key":"ref7","article-title":"Spiking Neuron Models","author":"wulfram","year":"2002","journal-title":"Cambridge University Press"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577381"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2018.00291"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2014.42"}],"event":{"name":"2018 Conference on Design and Architectures for Signal and Image Processing (DASIP)","start":{"date-parts":[[2018,10,10]]},"location":"Porto","end":{"date-parts":[[2018,10,12]]}},"container-title":["2018 Conference on Design and Architectures for Signal and Image Processing (DASIP)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8587115\/8596834\/08597119.pdf?arnumber=8597119","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,25]],"date-time":"2022-01-25T19:43:09Z","timestamp":1643139789000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8597119\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/dasip.2018.8597119","relation":{},"subject":[],"published":{"date-parts":[[2018,10]]}}}