{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T12:31:01Z","timestamp":1742387461204,"version":"3.28.0"},"reference-count":30,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/date.2003.1186386","type":"proceedings-article","created":{"date-parts":[[2003,12,22]],"date-time":"2003-12-22T12:34:10Z","timestamp":1072096450000},"page":"196-203","source":"Crossref","is-referenced-by-count":3,"title":["Exact high level WCET analysis of synchronous programs by symbolic state space exploration"],"prefix":"10.1109","author":[{"given":"G.","family":"Logothetis","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"K.","family":"Schneider","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Jester Home Page","year":"0","key":"19"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1145\/235321.235322"},{"key":"18","article-title":"A general approach for the tight timing predictions of non-rectangular loops","author":"healy","year":"1999","journal-title":"IEEE Real-Time Technology and Applications Symposium"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-2231-4"},{"journal-title":"Embedded Market Breaks New Ground","year":"2000","author":"halfhill","key":"16"},{"key":"13","doi-asserted-by":"crossref","first-page":"1298","DOI":"10.1007\/BFb0002886","article-title":"Deriving annotations for tight calculation of execution time","volume":"1300","author":"ermedahl","year":"1997","journal-title":"International European Conference on Parallel Processing (EuroPar"},{"key":"14","article-title":"Compilation and timing analysis of statecharts models for embedded systems","author":"erpenbach","year":"1999","journal-title":"Proc Int Conf Compilers Architecture and Synthesis Embedded Systems (CASES)"},{"key":"11","doi-asserted-by":"crossref","DOI":"10.1007\/3-540-44585-4_39","article-title":"Taxys: A tool for the developpment and verification real-Time embedded systems","volume":"2102","author":"closse","year":"2001","journal-title":"Computer Aided Verification (CAV"},{"journal-title":"ECL Homepage","year":"0","key":"12"},{"key":"21","doi-asserted-by":"crossref","DOI":"10.1007\/BFb0057778","article-title":"Automatic accurate time-bound analysis for high-level languages","author":"liu","year":"1998","journal-title":"Languages Compilers and Tools for Embedded Systems (LCTES"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1145\/7351.7352"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/EMRTS.2001.934025"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2002.998390"},{"key":"24","doi-asserted-by":"crossref","DOI":"10.1007\/BFb0057776","article-title":"Integrating path and timing analysis using instruction-level simulation techniques","author":"lundqvist","year":"1998","journal-title":"Languages Compilers and Tools for Embedded Systems (LCTES"},{"journal-title":"Embedded Processor Forum","year":"0","key":"25"},{"key":"26","first-page":"16","article-title":"Worst-case execution time analysis at low cost","author":"puschner","year":"1997","journal-title":"Distributed Computer Control Systems"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1007\/BF00571421"},{"key":"28","first-page":"205","article-title":"A verified hardware synthesis for esterel","author":"schneider","year":"2000","journal-title":"International IFIP Workshop on Distributed and Parallel Embedded Systems"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/CSD.2001.981772"},{"journal-title":"The Constructive Semantics of Pure Esterel","year":"1999","author":"berry","key":"3"},{"key":"2","article-title":"The foundations of esterel","author":"berry","year":"1998","journal-title":"Proof Language and Interaction Essays in Honour of Robin Milner"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-61474-5_74"},{"key":"1","article-title":"An approach to symbolic worstcase execution time analysis","author":"bernat","year":"2000","journal-title":"IFAC Workshop on Real-Time Programming"},{"key":"30","article-title":"Realizing real-Time systems from synchronous language specifications","author":"shyamasundar","year":"2000","journal-title":"Real Time Systems Symposium"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676819"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/.2001.980712"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1990.130210"},{"journal-title":"The Esterel v5-91 Language Primer","year":"2000","author":"berry","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/216636.216661"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1016\/0890-5401(92)90017-A"}],"event":{"name":"6th Design Automation and Test in Europe (DATE 03)","acronym":"DATE-03","location":"Munich, Germany"},"container-title":["2003 Design, Automation and Test in Europe Conference and Exhibition"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8443\/26600\/01186386.pdf?arnumber=1186386","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,3,28]],"date-time":"2020-03-28T04:22:55Z","timestamp":1585369375000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1186386\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":30,"URL":"https:\/\/doi.org\/10.1109\/date.2003.1186386","relation":{},"subject":[]}}