{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,13]],"date-time":"2026-03-13T12:56:24Z","timestamp":1773406584972,"version":"3.50.1"},"reference-count":18,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/date.2004.1268846","type":"proceedings-article","created":{"date-parts":[[2004,6,21]],"date-time":"2004-06-21T21:52:40Z","timestamp":1087854760000},"page":"182-187","source":"Crossref","is-referenced-by-count":33,"title":["Graph-based functional test program generation for pipelined processors"],"prefix":"10.1109","author":[{"given":"P.","family":"Mishra","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N.","family":"Dutt","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1980.1675602"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1999.781305"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1145\/309847.309908"},{"key":"16","article-title":"Formal verification of out-of-order execution using incremental Flushing","author":"skakkebaek","year":"1998","journal-title":"CAV"},{"key":"13","article-title":"Functional abstraction driven design space exploration of Heterogeneous Programmable Architectures","author":"mishra","year":"2001","journal-title":"ISSS"},{"key":"14","article-title":"Trace table based approach for pipelined microprocessor Verification","author":"sawada","year":"1997","journal-title":"CAV"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1145\/378239.378282"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2002.1224436"},{"key":"3","doi-asserted-by":"crossref","DOI":"10.1145\/309847.309912","article-title":"High-level test generation for design verification of pipelined Microprocessors","author":"campenhout","year":"1999","journal-title":"DAC"},{"key":"2","article-title":"Automatic verification of pipelined microprocessor control","author":"burch","year":"1994","journal-title":"CAV"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1145\/217474.217542"},{"key":"10","article-title":"Microarchitecture verification by compositional model checking","author":"jhala","year":"2001","journal-title":"CAV"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/288548.289082"},{"key":"6","author":"hennessy","year":"1990","journal-title":"Computer Architecture A Quantitative Approach"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/307418.307549"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2003.1219068"},{"key":"9","article-title":"Automatic test pattern generation for pipelined processors","author":"iwashita","year":"1994","journal-title":"ICCAD"},{"key":"8","year":"0","journal-title":"Symbolic Model Verifier"}],"event":{"name":". Design, Automation and Test in Europe Conference and Exhibition","location":"Paris, France","acronym":"DATE-04"},"container-title":["Proceedings Design, Automation and Test in Europe Conference and Exhibition"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8959\/28390\/01268846.pdf?arnumber=1268846","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,17]],"date-time":"2024-12-17T16:59:03Z","timestamp":1734454743000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1268846\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/date.2004.1268846","relation":{},"subject":[]}}