{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T00:01:04Z","timestamp":1773187264298,"version":"3.50.1"},"reference-count":13,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/date.2004.1268852","type":"proceedings-article","created":{"date-parts":[[2004,6,21]],"date-time":"2004-06-21T21:52:40Z","timestamp":1087854760000},"page":"220-225","source":"Crossref","is-referenced-by-count":6,"title":["Using a victim buffer in an application-specific memory hierarchy"],"prefix":"10.1109","author":[{"family":"Chuanjun Zhang","sequence":"first","affiliation":[]},{"given":"F.","family":"Vahid","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"13","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859635"},{"key":"11","article-title":"Low power design techniques for microprocessors","author":"segars","year":"2001","journal-title":"IEEE Int Solid-State Circuits Conf Tutorial"},{"key":"12","year":"0","journal-title":"Tensilica Inc"},{"key":"3","year":"0","journal-title":"ARC International"},{"key":"2","article-title":"Selective cache ways: On-demand cache resource allocation","author":"albonesi","year":"2000","journal-title":"Journal of Instruction Level Parallelism"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/LPD.1999.750402"},{"key":"10","year":"0","journal-title":"MIPS Technologies Inc"},{"key":"7","doi-asserted-by":"crossref","DOI":"10.1145\/325096.325162","article-title":"Improving direct-mapped cache performance by the addition of a small fully-Associative cache and prefetch buffers","author":"jouppi","year":"1990","journal-title":"Proc International Symposium on Computer Architecture"},{"key":"6","year":"0"},{"key":"5","author":"burger","year":"1997","journal-title":"The SimpleScalar Tool Set"},{"key":"4","year":"0","journal-title":"ARM Ltd"},{"key":"9","doi-asserted-by":"crossref","first-page":"241","DOI":"10.1145\/344166.344610","article-title":"a low power unified cache architecture providing power and performance flexibility","author":"malik","year":"2000","journal-title":"ISLPED 00 the 2000 International Symposium on Low Power Electronics and Design (Cat No 00TH8514) LPE-00"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645830"}],"event":{"name":". Design, Automation and Test in Europe Conference and Exhibition","location":"Paris, France","acronym":"DATE-04"},"container-title":["Proceedings Design, Automation and Test in Europe Conference and Exhibition"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8959\/28390\/01268852.pdf?arnumber=1268852","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,6,3]],"date-time":"2018-06-03T12:39:08Z","timestamp":1528029548000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1268852\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/date.2004.1268852","relation":{},"subject":[]}}