{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,9]],"date-time":"2026-07-09T01:59:22Z","timestamp":1783562362907,"version":"3.55.0"},"reference-count":9,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/date.2004.1268856","type":"proceedings-article","created":{"date-parts":[[2004,6,21]],"date-time":"2004-06-21T17:52:40Z","timestamp":1087840360000},"page":"246-251","source":"Crossref","is-referenced-by-count":431,"title":["A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation"],"prefix":"10.1109","author":[{"given":"K.","family":"Tiri","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"I.","family":"Verbauwhede","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"3","first-page":"125","article-title":"Securing encryption algorithms against dpa at the logic level: Next generation smart card technology","author":"tiri","year":"2003","journal-title":"CHES"},{"key":"2","doi-asserted-by":"crossref","first-page":"388","DOI":"10.1007\/3-540-48405-1_25","article-title":"Differential power analysis","author":"kocher","year":"1999","journal-title":"Advances in CryptologyCRYPTO '99 Proc"},{"key":"1","first-page":"55","article-title":"Information leakage attacks against smart card implementations of cryptographic algorithms and countermeasures-A survey","author":"hess","year":"2000","journal-title":"Eurosmart Security Conference"},{"key":"7","year":"0","journal-title":"Avnet Design Services Xilinx Virtex-II Development Kit"},{"key":"6","year":"2002","journal-title":"Xilinx Vertex II Platform FPGAs Detailed Description"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2000.896507"},{"key":"4","first-page":"403","article-title":"A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards","author":"tiri","year":"2002","journal-title":"Proceedings of the 28th European Solid-State Circuits Conference ESSCIRC"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/775844.775845"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253591"}],"event":{"name":". Design, Automation and Test in Europe Conference and Exhibition","location":"Paris, France","acronym":"DATE-04"},"container-title":["Proceedings Design, Automation and Test in Europe Conference and Exhibition"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8959\/28390\/01268856.pdf?arnumber=1268856","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T04:12:14Z","timestamp":1497586334000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1268856\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/date.2004.1268856","relation":{},"subject":[]}}