{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T19:52:19Z","timestamp":1725652339543},"reference-count":7,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/date.2004.1268869","type":"proceedings-article","created":{"date-parts":[[2004,6,21]],"date-time":"2004-06-21T21:52:40Z","timestamp":1087854760000},"page":"332-337","source":"Crossref","is-referenced-by-count":2,"title":["How can system level design solve the interconnect technology scaling problem?"],"prefix":"10.1109","author":[{"given":"F.","family":"Catthoor","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Cuomo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.","family":"Martin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.","family":"Groeneveld","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L.","family":"Rudy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"K.","family":"Maex","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.","family":"van de Steeg","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.","family":"Wilson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/581199.581221"},{"key":"2","doi-asserted-by":"crossref","DOI":"10.1145\/639929.639954","article-title":"Global interconnect trade-off for technology over memory modules to application level: Case study'', {\\em 5th ACM\/","author":"papanikolaou","year":"2003","journal-title":"IEEE Intnl \\ Wsh \\ on System Level Interconnect Prediction"},{"journal-title":"A Survey of Design Techniques for System-level Dynamic Power management'' \\Em","year":"2000","author":"benini","key":"1"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/MEMCOD.2003.1210113"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.1995.499187"},{"journal-title":"Managing Wire Scaling A Circuit Perspective","year":"0","author":"ho","key":"5"},{"key":"4","doi-asserted-by":"crossref","first-page":"208","DOI":"10.1109\/MICRO.2002.1176251","article-title":"Compiler-directed instruction cache leakage optimization","author":"zhang","year":"2002","journal-title":"Proc \\ IEEE\/ACM Intnl \\ Symp \\ on Microarchitecture (MICRO-35)"}],"event":{"name":". Design, Automation and Test in Europe Conference and Exhibition","acronym":"DATE-04","location":"Paris, France"},"container-title":["Proceedings Design, Automation and Test in Europe Conference and Exhibition"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8959\/28390\/01268869.pdf?arnumber=1268869","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,4,28]],"date-time":"2023-04-28T21:57:02Z","timestamp":1682719022000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1268869\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/date.2004.1268869","relation":{},"subject":[]}}