{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,24]],"date-time":"2025-03-24T06:44:05Z","timestamp":1742798645008},"reference-count":18,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/date.2004.1268894","type":"proceedings-article","created":{"date-parts":[[2004,6,21]],"date-time":"2004-06-21T17:52:40Z","timestamp":1087840360000},"page":"494-499","source":"Crossref","is-referenced-by-count":6,"title":["Simultaneous state, Vt and Tox assignment for total standby power minimization"],"prefix":"10.1109","author":[{"family":"Dongwoo Lee","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"H.","family":"Deogun","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.","family":"Blaauw","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.","family":"Sylvester","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Watson Research Personalcommunication","year":"0","author":"puri","key":"17"},{"key":"18","first-page":"695","article-title":"A Neutral netlist of 10combinational benchmark circuits","author":"brglez","year":"1985","journal-title":"Proc ISCAS"},{"key":"15","first-page":"90","article-title":"Limits of gate oxide scaling in nano-transistors","author":"yu","year":"2000","journal-title":"Proc Symp VLSI Tech"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/55.877204"},{"journal-title":"International Technology Roadmap for Semiconductors","year":"2002","key":"13"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/16.853042"},{"journal-title":"Optimizing Performance and Power for 130nm and Beyond","year":"2003","author":"stiffler","key":"11"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775881"},{"key":"3","article-title":"Techniques for leakage power reduction","author":"de","year":"2001","journal-title":"Design of High-Performance Microprocessor Circuits"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/4.400426"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1997.606670"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2002.1167561"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/566421.566425"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2003.1194710"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/775876.775878"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/43.766723"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/92.994980"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2000.852696"}],"event":{"name":". Design, Automation and Test in Europe Conference and Exhibition","acronym":"DATE-04","location":"Paris, France"},"container-title":["Proceedings Design, Automation and Test in Europe Conference and Exhibition"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8959\/28390\/01268894.pdf?arnumber=1268894","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T13:00:43Z","timestamp":1489410043000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1268894\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/date.2004.1268894","relation":{},"subject":[]}}