{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,6]],"date-time":"2026-10-06T10:50:09Z","timestamp":1791283809556,"version":"4.1.0"},"reference-count":29,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/date.2004.1268998","type":"proceedings-article","created":{"date-parts":[[2004,6,21]],"date-time":"2004-06-21T17:52:40Z","timestamp":1087840360000},"page":"878-883","source":"Crossref","is-referenced-by-count":36,"title":["An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration"],"prefix":"10.1109","author":[{"given":"A.","family":"Radulescu","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"J.","family":"Dielissen","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"K.","family":"Goossens","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"E.","family":"Rijpkema","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"P.","family":"Wielage","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"19","article-title":"Philips Semiconductors","year":"2002","journal-title":"Device Transaction Level (DTL) Protocol Specification"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2002.1016885"},{"key":"18","article-title":"OCP International Partnership","year":"2003","journal-title":"Open Core Protocol Specification 2 0 Release Candidate"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.1044298"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/43.898830"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1007\/0-306-48727-6_4"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2000.840047"},{"key":"11","article-title":"Cost-performance trade-offs in networks on chip: A simulation based approach","author":"gonzalez pestana","year":"2004","journal-title":"Proc DATE"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2002.998309"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253633"},{"key":"20","article-title":"Tailoring Router Architectures to Performance Requirements in Cut-Through Networks","author":"rexford","year":"1999","journal-title":"PhD thesis"},{"key":"22","author":"rose","year":"1990","journal-title":"The Open Book A Practical Perspective on OSI"},{"key":"23","article-title":"Communication services for networks on chip","author":"radulescu","year":"2003","journal-title":"Domain-specific Embedded Multiprocessors"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379045"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1145\/244764.244767"},{"key":"26","author":"tanenbaum","year":"1996","journal-title":"Computer Networks"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2003.1213180"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1109\/SBCCI.2002.1137647"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/5.469298"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"2","doi-asserted-by":"crossref","first-page":"33","DOI":"10.1145\/500001.500009","article-title":"powering networks on chips","author":"benini","year":"2001","journal-title":"International Symposium on System Synthesis (IEEE Cat No 01EX526) ISSS-01"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2003.1231972"},{"key":"1","article-title":"ARM","year":"2003","journal-title":"AMBA AXI Protocol Specification"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/2.730735"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/223982.224434"},{"key":"5","article-title":"QNoC: QoS architecture and design process for network on chip","volume":"49","author":"bolotin","year":"2003","journal-title":"Journal of Systems Architecture"},{"key":"4","article-title":"Interfacing cores with on-chip packet-switched networks","author":"bhojwani","year":"2003","journal-title":"Proc VLSI Design"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"8","author":"culler","year":"1999","journal-title":"Parallel Computer Architecture A Hardware\/ Software Approach"}],"event":{"name":". Design, Automation and Test in Europe Conference and Exhibition","location":"Paris, France","acronym":"DATE-04"},"container-title":["Proceedings Design, Automation and Test in Europe Conference and Exhibition"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8959\/28391\/01268998.pdf?arnumber=1268998","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T04:12:15Z","timestamp":1497586335000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1268998\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":29,"URL":"https:\/\/doi.org\/10.1109\/date.2004.1268998","relation":{},"subject":[]}}