{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T02:29:43Z","timestamp":1729650583122,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/date.2004.1269112","type":"proceedings-article","created":{"date-parts":[[2004,7,20]],"date-time":"2004-07-20T10:08:28Z","timestamp":1090318108000},"page":"1412-1413","source":"Crossref","is-referenced-by-count":0,"title":["Placement using a localization probability model (LPM)"],"prefix":"10.1109","author":[{"given":"M.","family":"Olbrich","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E.","family":"Barke","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","first-page":"284","article-title":"A class of min-cut placement algorithms","volume":"77","author":"breuer","year":"1977","journal-title":"DAC"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/266021.266275"},{"key":"10","first-page":"260","article-title":"Dragon2000: Standard-cell placement tool for large industry circuits","volume":"0","author":"wang","year":"2000","journal-title":"ICCAD"},{"year":"0","key":"1"},{"key":"7","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4613-1697-8","author":"sechen","year":"1988","journal-title":"VLSI Placement and Global Routing Using Simulated Annealing"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1982.1585498"},{"key":"5","doi-asserted-by":"crossref","first-page":"269","DOI":"10.1145\/277044.277119","article-title":"Generic global placement and floorplanning","author":"eisenmann","year":"1998","journal-title":"Proceedings 1998 Design and Automation Conference 35th DAC (Cat No 98CH36175) DAC"},{"key":"4","first-page":"349","article-title":"Hypergraph partitioning for VLSI CAD","volume":"99","author":"caldwell","year":"1999","journal-title":"DAC"},{"key":"9","first-page":"54","article-title":"FPGA placement by thermodynamic combinatorial optimization","volume":"2","author":"vicente","year":"2002","journal-title":"DATE"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1993.580051"}],"event":{"name":"Design, Automation and Test in Europe Conference and Exhibition","acronym":"DATE-04","location":"Paris, France"},"container-title":["Proceedings Design, Automation and Test in Europe Conference and Exhibition"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8959\/28391\/01269112.pdf?arnumber=1269112","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T04:53:22Z","timestamp":1497588802000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1269112\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/date.2004.1269112","relation":{},"subject":[]}}