{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T00:32:15Z","timestamp":1729643535933,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,3]]},"DOI":"10.1109\/date.2008.4484779","type":"proceedings-article","created":{"date-parts":[[2008,4,15]],"date-time":"2008-04-15T22:15:51Z","timestamp":1208297751000},"page":"843-848","source":"Crossref","is-referenced-by-count":11,"title":["A Generic Standard Cell Design Methodology for Differential Circuit Styles"],"prefix":"10.1109","author":[{"given":"Stephane","family":"Badel","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Erdem","family":"Guleyupoglu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ozgur","family":"Inac","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anna Pena","family":"Martinez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paolo","family":"Vietti","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Frank K.","family":"Gurkaynak","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yusuf","family":"Leblebici","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052767"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2006.1693229"},{"key":"10","first-page":"1181","article-title":"an mos current mode logic (mcml) circuit for low-power sub-ghz processors","volume":"e75 c","author":"yamashina","year":"1992","journal-title":"IEICE transaction on Electronics"},{"key":"1","doi-asserted-by":"crossref","DOI":"10.1007\/1-4020-2888-1","author":"aliotto","year":"2005","journal-title":"Model and Design of Bipolar and MOS Current-Mode Logic CML ECL and SCL Digital Circuits"},{"key":"7","doi-asserted-by":"crossref","first-page":"209","DOI":"10.1109\/ICSAMOS.2007.4285753","article-title":"a simulation-based methodology for evaluating the dpa-resistance of cryptographic functional units with application to cmos and mcml technologies","author":"regazzoni","year":"2007","journal-title":"Embedded Computer Systems Architectures Modeling and Simulation 2007 IC-SAMOS 2007 International Conference on"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/4.509871"},{"year":"0","key":"5"},{"journal-title":"A new interconnect-centric design methodology for high-speed standard cells with crosstalk immunity","year":"2006","author":"hatirnaz","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/92.736130"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/4.508212"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/4.597298"}],"event":{"name":"2008 Design, Automation and Test in Europe","start":{"date-parts":[[2008,3,10]]},"location":"Munich, Germany","end":{"date-parts":[[2008,3,14]]}},"container-title":["2008 Design, Automation and Test in Europe"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4475437\/4484624\/04484779.pdf?arnumber=4484779","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,9,8]],"date-time":"2021-09-08T06:49:20Z","timestamp":1631083760000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4484779\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,3]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/date.2008.4484779","relation":{},"subject":[],"published":{"date-parts":[[2008,3]]}}}