{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T07:07:45Z","timestamp":1729667265809,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,4]]},"DOI":"10.1109\/date.2009.5090677","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T13:16:39Z","timestamp":1361279799000},"page":"304-307","source":"Crossref","is-referenced-by-count":6,"title":["Parallel transistor level full-chip circuit simulation"],"prefix":"10.1109","author":[{"family":"He Peng","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Chung-Kuan Cheng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"13","doi-asserted-by":"publisher","DOI":"10.1137\/1.9780898718881"},{"journal-title":"FWgrid","year":"0","key":"14"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1137\/1.9780898718003"},{"journal-title":"PETSc Users Manual ANL-95\/11","year":"0","author":"balay","key":"12"},{"key":"3","doi-asserted-by":"crossref","first-page":"238","DOI":"10.1145\/1391469.1391531","article-title":"wavepipe: parallel transient simulation of analog and digital circuits on multi-core shared-memory machines","author":"wei dong","year":"2008","journal-title":"2008 45th ACM\/IEEE Design Automation Conference DAC"},{"key":"2","first-page":"54","article-title":"parallel domain decomposition for simulation of large-scale power grids, in proc","author":"sun","year":"2007","journal-title":"ICCAD"},{"key":"1","article-title":"spice2: a computer program to simulate semiconductor circuits","author":"nagal","year":"1975","journal-title":"Tech Rep ERL"},{"journal-title":"Domain Decomposition Parallel Multilevel Methods for Elliptic Partial Differential Equations","year":"2004","author":"smith","key":"10"},{"key":"7","article-title":"the xyce parallel electronic simulator - an overview","author":"hutchinson","year":"2000","journal-title":"IEEE International Symposium on Circuits and Systems Sydney (AU)"},{"key":"6","article-title":"a new approach for parallel simulation of vlsi circuits on a transsitor level","volume":"45","author":"frohlich","year":"1998","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"5","first-page":"397","article-title":"parallel transistor level circuit simulation using domain decomposition methods, in proc","author":"peng","year":"2009","journal-title":"ASPDAC"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681554"},{"journal-title":"ParMETIS - Parallel Graph Partitioning and Sparse Matrix Ordering","year":"2003","author":"karypis","key":"9"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1002\/047134608X.W2528"}],"event":{"name":"2009 Design, Automation & Test in Europe Conference & Exhibition (DATE'09)","start":{"date-parts":[[2009,4,20]]},"location":"Nice","end":{"date-parts":[[2009,4,24]]}},"container-title":["2009 Design, Automation &amp; Test in Europe Conference &amp; Exhibition"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4926138\/5090609\/05090677.pdf?arnumber=5090677","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T03:48:10Z","timestamp":1498016890000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5090677\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,4]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/date.2009.5090677","relation":{},"subject":[],"published":{"date-parts":[[2009,4]]}}}