{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T15:02:55Z","timestamp":1730214175306,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,4]]},"DOI":"10.1109\/date.2009.5090690","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T18:16:39Z","timestamp":1361297799000},"page":"369-373","source":"Crossref","is-referenced-by-count":3,"title":["Power reduction of a 12-bit 40-MS\/s pipeline ADC exploiting partial amplifier sharing"],"prefix":"10.1109","author":[{"given":"J. A.","family":"Diaz-Madrid","sequence":"first","affiliation":[{"name":"Integrated Circuit Design - Analog, Fraunhofer Institute for Integrated Circuits, Erlangen, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"H.","family":"Neubauer","sequence":"additional","affiliation":[{"name":"Integrated Circuit Design - Analog, Fraunhofer Institute for Integrated Circuits, Erlangen, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"H.","family":"Hauer","sequence":"additional","affiliation":[{"name":"Integrated Circuit Design - Analog, Fraunhofer Institute for Integrated Circuits, Erlangen, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.","family":"Domenech-Asensi","sequence":"additional","affiliation":[{"name":"Dpto. de Electr\u00f3nica y Tecnolog\u00eda de Computadoras, Universidad Polit\u00e9cnica de Cartagena, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.","family":"Ruiz-Merino","sequence":"additional","affiliation":[{"name":"Dpto. de Electr\u00f3nica y Tecnolog\u00eda de Computadoras, Universidad Polit\u00e9cnica de Cartagena, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"0","key":"13"},{"key":"11","article-title":"comparative analysis of two operational amplifier topologies for a 40ms\/s 12-bit pipelined adc in 0.35m cmos","author":"diaz","year":"2008","journal-title":"Intl Conf on IC Design and Technology ICICDT"},{"year":"0","key":"12"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/4.545805"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/4.494191"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/4.364429"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2003.820253"},{"journal-title":"CMOS Mixed-Signal Circuit Design","year":"2002","author":"baker","key":"7"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/4.760369"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.873888"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.819166"},{"key":"9","first-page":"1457","article-title":"analysis and design of fully differential gainboosted telescopic cascode opamp","volume":"2","author":"jin","year":"2004","journal-title":"IEEE J Solid State Circuits"},{"year":"0","key":"8"}],"event":{"name":"2009 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2009,4,20]]},"location":"Nice, France","end":{"date-parts":[[2009,4,24]]}},"container-title":["2009 Design, Automation & Test in Europe Conference & Exhibition"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4926138\/5090609\/05090690.pdf?arnumber=5090690","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,6,8]],"date-time":"2021-06-08T09:12:41Z","timestamp":1623143561000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/5090690\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,4]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/date.2009.5090690","relation":{},"subject":[],"published":{"date-parts":[[2009,4]]}}}