{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,21]],"date-time":"2025-11-21T11:24:35Z","timestamp":1763724275691},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,4]]},"DOI":"10.1109\/date.2009.5090727","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T13:16:39Z","timestamp":1361279799000},"page":"562-565","source":"Crossref","is-referenced-by-count":23,"title":["Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints"],"prefix":"10.1109","author":[{"given":"D.","family":"Ludovici","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"F.","family":"Gilabert","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Medardoni","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"C.","family":"Gomez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.E.","family":"Gomez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.","family":"Lopez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.N.","family":"Gaydadjiev","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.","family":"Bertozzi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"17","first-page":"559","author":"stergiou","year":"2005","journal-title":"Xpipes Lite A Synthesis Oriented Design Library for Networks on Chips"},{"journal-title":"Circuits Multi-Projects Multi-Project Circuits","year":"0","key":"15"},{"year":"0","key":"16"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.134"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1145\/1081081.1081138"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2008.4492730"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/IPPS.1997.580853"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2002.1016885"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"year":"0","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2008.8"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378785"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/I-SPAN.2008.39"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/299996.300073"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253633"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2007.370482"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253808"}],"event":{"name":"2009 Design, Automation & Test in Europe Conference & Exhibition (DATE'09)","start":{"date-parts":[[2009,4,20]]},"location":"Nice","end":{"date-parts":[[2009,4,24]]}},"container-title":["2009 Design, Automation & Test in Europe Conference & Exhibition"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4926138\/5090609\/05090727.pdf?arnumber=5090727","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,18]],"date-time":"2017-03-18T00:55:45Z","timestamp":1489798545000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5090727\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,4]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/date.2009.5090727","relation":{},"subject":[],"published":{"date-parts":[[2009,4]]}}}