{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T14:04:02Z","timestamp":1725631442862},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,4]]},"DOI":"10.1109\/date.2009.5090744","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T13:16:39Z","timestamp":1361279799000},"page":"634-639","source":"Crossref","is-referenced-by-count":13,"title":["Evaluation on FPGA of triple rail logic robustness against DPA and DEMA"],"prefix":"10.1109","author":[{"given":"V.","family":"Lomne","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.","family":"Maurine","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L.","family":"Torres","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Robert","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.","family":"Soares","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N.","family":"Calazans","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"17","article-title":"near-field mapping system to scan in time domain the magnetic emissions of integrated circuits","author":"ordas","year":"2008","journal-title":"Proc 18th International Workshop on Power and Timing Modeling Optimization and Simulation (PATMOS)"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403685"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601950"},{"key":"13","first-page":"30","article-title":"power analysis of an fpga implementation of rijndael: is pipelining a dpa countermeasure?","author":"standaert","year":"2004","journal-title":"Proc 6th Workshop on Cryptographic Hardware and Embedded Systems (CHES)"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.855939"},{"key":"11","first-page":"125","article-title":"securing encryption algorithms against dpa at the logic level: next generation smart cards technology","author":"tiri","year":"2003","journal-title":"Proc 5th Workshop on Cryptographic Hardware and Embedded Systems (CHES)"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2005.18"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.61"},{"key":"2","first-page":"242","article-title":"dual-rail random switching logic: a countermeasure to reduce side channel leakage","author":"chen","year":"2006","journal-title":"Proc 8th Workshop on Cryptographic Hardware and Embedded Systems (CHES)"},{"key":"1","first-page":"388","article-title":"differential power analysis","author":"kocher","year":"1999","journal-title":"Proc 19th International Conference on Cryptology (CRYPTO)"},{"key":"10","first-page":"20","article-title":"secured structures for secured asynchronous qdi circuits","author":"razafindraibe","year":"2004","journal-title":"Proc 19th International Conference on Design of Circuits and Integrated Systems (DCIS)"},{"key":"7","first-page":"186","article-title":"a dynamic current mode logic to counteract power analysis attacks","author":"mace","year":"2004","journal-title":"Proc 19th International Conference on Design of Circuits and Integrated Systems (DCIS)"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1269113"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISOC.2007.4402510"},{"key":"4","first-page":"137","article-title":"security evaluation of asynchronous circuits","author":"fournier","year":"2003","journal-title":"Proc 5th Workshop on Cryptographic Hardware and Embedded Systems (CHES)"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.124"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2003.1199180"}],"event":{"name":"2009 Design, Automation & Test in Europe Conference & Exhibition (DATE'09)","start":{"date-parts":[[2009,4,20]]},"location":"Nice","end":{"date-parts":[[2009,4,24]]}},"container-title":["2009 Design, Automation &amp; Test in Europe Conference &amp; Exhibition"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4926138\/5090609\/05090744.pdf?arnumber=5090744","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,18]],"date-time":"2017-03-18T00:26:59Z","timestamp":1489796819000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5090744\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,4]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/date.2009.5090744","relation":{},"subject":[],"published":{"date-parts":[[2009,4]]}}}