{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,18]],"date-time":"2026-05-18T20:55:34Z","timestamp":1779137734536,"version":"3.51.4"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,4]]},"DOI":"10.1109\/date.2009.5090762","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T18:16:39Z","timestamp":1361297799000},"page":"737-742","source":"Crossref","is-referenced-by-count":23,"title":["Power and performance of read-write aware Hybrid Caches with non-volatile memories"],"prefix":"10.1109","author":[{"family":"Xiaoxia Wu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Jian Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Lixin Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E.","family":"Speight","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Yuan Xie","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"13","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605420"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1145\/225830.223990"},{"key":"11","doi-asserted-by":"crossref","first-page":"554","DOI":"10.1145\/1391469.1391610","article-title":"circuit and microarchitecture evaluation of 3d stacking magnetic ram (mram) as a universal memory replacement","author":"xiangyu dong","year":"2008","journal-title":"2008 45th ACM\/IEEE Design Automation Conference DAC"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609379"},{"key":"3","year":"2006"},{"key":"2","year":"0"},{"key":"1","year":"0"},{"key":"10","first-page":"132","article-title":"cell design considerations for phase change memory as a universal memory","author":"chung","year":"2008","journal-title":"VLSI-TSA"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.21"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1177\/109434209100500306"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2005.1526013"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/DRC.2005.1553042"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/1080695.1070001"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"}],"event":{"name":"2009 Design, Automation & Test in Europe Conference & Exhibition (DATE'09)","location":"Nice","start":{"date-parts":[[2009,4,20]]},"end":{"date-parts":[[2009,4,24]]}},"container-title":["2009 Design, Automation & Test in Europe Conference & Exhibition"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4926138\/5090609\/05090762.pdf?arnumber=5090762","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T07:48:09Z","timestamp":1498031289000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5090762\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,4]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/date.2009.5090762","relation":{},"subject":[],"published":{"date-parts":[[2009,4]]}}}