{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,3]],"date-time":"2025-06-03T15:15:39Z","timestamp":1748963739754,"version":"3.28.0"},"reference-count":21,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,4]]},"DOI":"10.1109\/date.2009.5090862","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T13:16:39Z","timestamp":1361279799000},"page":"1279-1283","source":"Crossref","is-referenced-by-count":1,"title":["Defect-aware logic mapping for nanowire-based programmable logic arrays via satisfiability"],"prefix":"10.1109","author":[{"family":"Yexin Zheng","sequence":"first","affiliation":[]},{"family":"Chao Huang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2003.818327"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2001.156196"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2002.998262"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/92.678873"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/12.769433"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2001.915010"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1999.781333"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147093"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2005.1560150"},{"journal-title":"ACM\/SIGDA benchmarks 1993 LGSynth Benchmarks","year":"0","key":"21"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1126\/science.291.5504.630"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2006.869684"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1007\/b116438"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2005.1560097"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2004.1393250"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2001.937446"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2008.0128"},{"key":"5","doi-asserted-by":"crossref","first-page":"1716","DOI":"10.1126\/science.280.5370.1716","article-title":"a defect-tolerant computer architecture: opportunities for nan-otechnology","volume":"280","author":"heath","year":"1998","journal-title":"Science"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/2.895116"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/14\/4\/311"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2007.907860"}],"event":{"name":"2009 Design, Automation & Test in Europe Conference & Exhibition (DATE'09)","start":{"date-parts":[[2009,4,20]]},"location":"Nice","end":{"date-parts":[[2009,4,24]]}},"container-title":["2009 Design, Automation & Test in Europe Conference & Exhibition"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4926138\/5090609\/05090862.pdf?arnumber=5090862","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T03:48:07Z","timestamp":1498016887000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5090862\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,4]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/date.2009.5090862","relation":{},"subject":[],"published":{"date-parts":[[2009,4]]}}}