{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T07:18:38Z","timestamp":1725520718727},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,3]]},"DOI":"10.1109\/date.2010.5456902","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T13:16:33Z","timestamp":1361279793000},"page":"993-996","source":"Crossref","is-referenced-by-count":2,"title":["Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits"],"prefix":"10.1109","author":[{"given":"Farhad","family":"Mehdipour","sequence":"first","affiliation":[]},{"given":"Hiroaki","family":"Honda","sequence":"additional","affiliation":[]},{"given":"Hiroshi","family":"Kataoka","sequence":"additional","affiliation":[]},{"given":"Koji","family":"Inoue","sequence":"additional","affiliation":[]},{"given":"Irina","family":"Kataeva","sequence":"additional","affiliation":[]},{"given":"Kazuaki","family":"Murakami","sequence":"additional","affiliation":[]},{"given":"Hiroyuki","family":"Akaike","sequence":"additional","affiliation":[]},{"given":"Akira","family":"Fujimaki","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/77.80745"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2009.2018534"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1063\/1.450106"},{"key":"ref5","article-title":"GRAPE-DR: 2-Pflops massively-computer with 512-core, 512-Gflops processor chips for scientific computing","author":"makino","year":"2008","journal-title":"Proc of Supercomputing"},{"article-title":"Algorithms for VLSI physical design automation","year":"1999","author":"sherwani","key":"ref8"},{"article-title":"Numerical recipes in C","year":"1988","author":"press","key":"ref7"},{"journal-title":"Synthesis and Optimization of Digital Circuits McGraw 1994","year":"0","author":"de micheli","key":"ref2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1093\/ietele\/e91-c.3.350"},{"journal-title":"ClearSpeed Processor","year":"0","key":"ref1"}],"event":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","start":{"date-parts":[[2010,3,8]]},"location":"Dresden","end":{"date-parts":[[2010,3,12]]}},"container-title":["2010 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE 2010)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5450668\/5456897\/05456902.pdf?arnumber=5456902","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,18]],"date-time":"2017-03-18T15:17:36Z","timestamp":1489850256000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5456902\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,3]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/date.2010.5456902","relation":{},"subject":[],"published":{"date-parts":[[2010,3]]}}}