{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,23]],"date-time":"2026-04-23T14:47:56Z","timestamp":1776955676408,"version":"3.51.4"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,3]]},"DOI":"10.1109\/date.2010.5456946","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T13:16:33Z","timestamp":1361279793000},"page":"777-782","source":"Crossref","is-referenced-by-count":21,"title":["KL-Cuts: A new approach for logic synthesis targeting multiple output blocks"],"prefix":"10.1109","author":[{"given":"Osvaldo","family":"Martinello","sequence":"first","affiliation":[]},{"given":"Felipe S.","family":"Marques","sequence":"additional","affiliation":[]},{"given":"Renato P.","family":"Ribas","sequence":"additional","affiliation":[]},{"given":"Andre I.","family":"Reis","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117208"},{"key":"ref11","article-title":"ABC: A System for Sequential Gynthesis and Verification","year":"0"},{"key":"ref12","article-title":"Achieving Higher System Performance with the Virtex-5 Family of FPGAs","year":"2006"},{"key":"ref13","article-title":"Improving FPGA Performance and Area Using an Adaptive Logic Module","year":"2004"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508152"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275118"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296425"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681549"},{"key":"ref5","article-title":"DAG-Aware AIG Rewriting: A Fresh Look at Combinational Logic Synthesis","author":"mishchenko","year":"2006","journal-title":"Design Automation Conference"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2007.4397320"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2006.320078"},{"key":"ref2","article-title":"Scalable Logic Synthesis using a Simple Circuit Structure","author":"mishchenko","year":"0","journal-title":"International Workship on Logic Synthesis"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.915545"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2007.5"}],"event":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","location":"Dresden","start":{"date-parts":[[2010,3,8]]},"end":{"date-parts":[[2010,3,12]]}},"container-title":["2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5450668\/5456897\/05456946.pdf?arnumber=5456946","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,2,5]],"date-time":"2020-02-05T15:56:22Z","timestamp":1580918182000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/5456946\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,3]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/date.2010.5456946","relation":{},"subject":[],"published":{"date-parts":[[2010,3]]}}}