{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,26]],"date-time":"2025-09-26T13:40:28Z","timestamp":1758894028296,"version":"3.28.0"},"reference-count":30,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,3]]},"DOI":"10.1109\/date.2010.5456948","type":"proceedings-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T18:16:33Z","timestamp":1361297793000},"page":"765-770","source":"Crossref","is-referenced-by-count":8,"title":["An error-correcting unordered code and hardware support for robust asynchronous global communication"],"prefix":"10.1109","author":[{"given":"Melinda Y","family":"Agyekum","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steven M","family":"Nowick","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2001.968598"},{"journal-title":"Globally-Asynchronous Locally-Synchronous Sys-tems","year":"1984","author":"chapiro","key":"ref10"},{"key":"ref11","first-page":"24","article-title":"Efficient systematic error-correcting codes for semi-delay-insensitive data transmission","author":"cheng","year":"2001","journal-title":"ICCD"},{"key":"ref12","first-page":"55","article-title":"Efficient self-timing with level-encoded 2-phase dual-rail (LEDR)","author":"dean","year":"1991","journal-title":"Proc Santa Cruz Conf Advanced Research in VLSI"},{"key":"ref13","first-page":"779","article-title":"Leakage-and crosstalk-aware bus encoding for total power reduction","author":"deogun","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1950.tb00463.x"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/43.24885"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/43.898830"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2008.24"},{"key":"ref18","first-page":"1","article-title":"Global delay optimization using structural choices","author":"mishchenko","year":"2008","journal-title":"IWLS"},{"key":"ref19","first-page":"278","article-title":"Design of self-checking asynchronous sequential circuits","author":"nanya","year":"1980","journal-title":"FTCS"},{"journal-title":"Asynchronous Sequential Switching Circuits","year":"1983","author":"unger","key":"ref28"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"68","DOI":"10.1016\/S0019-9958(61)80037-5","volume":"4","author":"berger","year":"1961","journal-title":"Information and Control"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2007.151"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2003.1199173"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1992.243585"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1007\/BF01788562"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2002.998256"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"521","DOI":"10.1109\/TC.1982.1676034","volume":"31","author":"bose","year":"1982","journal-title":"IEEE Trans on Comp"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/12.73583"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1973.223705"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"660","DOI":"10.1109\/12.381951","article-title":"Delay-insensitive pipelined communication on parallel buses","volume":"44","author":"bruck","year":"1995","journal-title":"IEEE Trans on Comp"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/12.709380"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1450135.1450182"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.827565"},{"key":"ref21","first-page":"96","volume":"27","author":"owens","year":"2007","journal-title":"Research challenges for on-chip interconnection net-works IEEE Micro"},{"year":"1992","author":"sentovich","key":"ref24"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1995.466975"},{"journal-title":"ABC A System for Sequential Synthesis and Verification","year":"2005","key":"ref26"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/92.365453"}],"event":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","start":{"date-parts":[[2010,3,8]]},"location":"Dresden","end":{"date-parts":[[2010,3,12]]}},"container-title":["2010 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE 2010)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5450668\/5456897\/05456948.pdf?arnumber=5456948","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T07:48:11Z","timestamp":1498031291000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5456948\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,3]]},"references-count":30,"URL":"https:\/\/doi.org\/10.1109\/date.2010.5456948","relation":{},"subject":[],"published":{"date-parts":[[2010,3]]}}}